Fujitsu FR60 Hardware Manual page 81

❍ Disabling the instruction cache (OFF)
To disable the instruction cache, set the ENAB bit to "0".
ldi #0x000003E7, r0
ldi #0B00000000, r1
stb r1, @r0
In this state maintained (which is the same as after reset), the instruction cache virtually does
not exist and thus does nothing.
It may be a good idea to turn off the instruction cache if overhead seems to be a problem.
❍ Locking the complete contents of the cache
Lock the instruction cache so that all the instructions it contains are removed, leaving nothing in
it.
Set the GBLK bit of the register to "1". Also set the ENAB bit to "1", since otherwise the instruction
cache is turned off and no locked instructions in the instruction cache are used.
ldi #0x000003E7, r0
ldi #0B00100001, r1
stb r1, @r0
CHAPTER 3 CPU AND CONTROL UNITS
// I-Cache control register address
// ENAB bit (Bit 0)
// Write to the register
// I-Cache control register address
// ENAB bit (Bit 0)
// GBLK bit (Bit 5)
// Write to the register
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