Fujitsu FR60 Hardware Manual page 106

CHAPTER 3 CPU AND CONTROL UNITS
Table 3.10-4 Vector Table (2 / 3)
Interrupt source
UART2 (reception completed)
UART0 (transmission completed)
UART1 (transmission completed)
UART2 (transmission completed)
DMAC0 (end, error)
DMAC1 (end, error)
DMAC2 (end, error)
DMAC3 (end, error)
DMAC4 (end, error)
A/D
PPG0
PPG1
PPG2
PPG3
Reserved for system
U-TIMER0
U-TIMER1
U-TIMER2
Time-base timer overflow
2
I C I/F0
2
I C I/F1
Reserved for system
Reserved for system
16bit free run timer
ICU0 (fetch)
ICU1 (fetch)
ICU2 (fetch)
ICU3 (fetch)
Reserved for system
Reserved for system
Reserved for system
86
Interrupt number
Decimal Hexadecimal
29 1D
30 1E
31 1F
32 20
33 21
34 22
35 23
36 24
37 25
38 26
39 27
40 28
41 29
42 2A
43 2B
44 2C
45 2D
46 2E
47 2F
48 30
49 31
50 32
51 33
52 34
53 35
54 36
55 37
56 38
57 39
58 3A
59 3B
Interrupt
Offset address of
level
ICR13 388 000FFF88
H
ICR14 384 000FFF84
H
ICR15 380 000FFF80
H
ICR16 37C 000FFF7C
H
ICR17 378 000FFF78
H
ICR18 374 000FFF74
H
ICR19 370 000FFF70
H
ICR20 36C 000FFF6C
H
ICR21 368 000FFF68
H
ICR22 364 000FFF64
H
ICR23 360 000FFF60
H
ICR24 35C 000FFF5C
H
ICR25 358 000FFF58
H
ICR26 354 000FFF54
H
ICR27 350 000FFF50
H
ICR28 34C 000FFF4C
H
ICR29 348 000FFF48
H
ICR30 344 000FFF44
H
ICR31 340 000FFF40
H
ICR32 33C 000FFF3C
H
ICR33 338 000FFF38
H
ICR34 334 000FFF34
H
ICR35 330 000FFF30
H
ICR36 32C 000FFF2C
H
ICR37 328 000FFF28
H
ICR38 324 000FFF24
H
ICR39 320 000FFF20
H
ICR40 31C 000FFF1C
H
ICR41 318 000FFF18
H
ICR42 314 000FFF14
H
ICR43 310 000FFF10
H
Default
RN
TBR
2
H
3
H
4
H
5
H
-
H
-
H
-
H
-
H
-
H
15
H
13
H
14
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H
-
H