Fujitsu FR60 Hardware Manual page 344

CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER
■ Return Operation from STOP State
The following operation is performed on the current circuit when an external interrupt is used to
return from the STOP state.
● Procedure prior to STOP state transition
Setting a path for an external interrupt
It is necessary to set a path for inputting an external interrupt in order to release the STOP
state before the device enters the STOP state. The PFR register (Port Function Register) is
used to perform this procedure. In a normal state (state other than the STOP state), an
interrupt input path is already allocated. Therefore, the above procedure should be ignored.
However, the input path is controlled by the value of the PFR register in the STOP state.
Name of pin used to release STOP state
• Inputting an external interrupt
When returning from a STOP state, an external interrupt signal is ready to transmit an input
signal without synchronization. As soon as this interrupt signal becomes valid, the internal
STOP signal immediately starts to fall. At the same time, the external interrupt circuit is
switched to synchronize another level interrupt input.
● Regulator stabilization wait time
Once the internal STOP signal falls, the STOP regulator is switched to the RUN regulator. A
stabilization wait time is secured for the internal output voltage because the operation becomes
unstable when the internal operation starts before the output voltage of the RUN Regulator
stabilizes. The clock is stopped during this period.
● Oscillator's oscillation time
The clock starts oscillating once the regulator stabilization wait time has passed. The oscillation
time varies depending of the oscillator used.
● Oscillation stabilization wait time
The oscillation stabilization wait time is taken within the device after the time. The oscillation
stabilization wait time is specified by the OS1 and OS0 bits in the standby control register. Once
the oscillation stabilization wait time has passed, an internal clock is supplied, an instruction
operation can be started by an external interrupt and any external interrupt source other than
the source for returning from the STOP state can be accepted.
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INT7/SCK2/PG7
INT6/SDT2/PG6
INT5/SIN2/PG5
INT4/ATG/PG4/FRCK
INT3/PG3/ICU3
INT2/PG2/ICU2
INT1/PG1/ICU1
INT0/PG0/ICU0
Register and bit to be set
Set bit 7 in PDRG to "0".
Set bit 6 in PDRG to "0".
Set bit 5 in PDRG to "0".
Set bit 4 in PDRG to "0".
Set bit 3 in PDRG to "0".
Set bit 2 in PDRG to "0".
Set bit 1 in PDRG to "0".
Set bit 0 in PDRG to "0".