Operation Of The Ordinary Bus Interface - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.5

Operation of the Ordinary Bus Interface

This section explains operation of the ordinary bus interface.
■ Ordinary Bus Interface
For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access
and write access.
The following operational phases of the ordinary bus interface are explained below with the use
of a timing chart.
• Basic timing (for successive accesses)
• WRn + byte control type
• Read -> write
• Write -> write
• Auto-wait cycle
• External wait cycle
• Synchronous write enable output
• CSn delay setting
• CSn -> RD/WRn setup, RD/WRn -> CSn hold setting
• DMA fly-by transfer (I/O -> memory)
• DMA fly-by transfer (memory -> I/O)
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