Fujitsu FR60 Hardware Manual page 143

■ Base Clock Division Setting Register 1 (DIVR1)
Figure 3.12-8 shows the configuration of the Base Clock Division Setting Register 1 (DIVR1)
bits.
Figure 3.12-8 Configuration of Base Clock Division Setting Register 1 (DIVR1) Bits
Address: 00000487
Initial value (INIT)
Initial value (RST)
Base Clock Division Setting Register 1 (DIVR1) controls the divide-by rate of an internal clock in
relation to the base clock. This register sets the divide-by rates of the external extended bus
interface clock (CLKT). An upper-limit frequency for operation is set for each clock. If you set a
combination of source clock, PLL multiply-by rate setting, and divide-by rate setting that results
in a frequency exceeding this upper-limit frequency, operation is not guaranteed. Be extra
careful of the order in which you change settings to select the source clock and to configure the
associated setting items.
If the setting in this register is changed, the new divide-by rate takes effect for the clock rate
following the one in which the setting was made.
[bit7 to bit4] T3, T2, T1, T0 (clkT divide select 3 to 0)
These bits are the clock divide-by rate setting bits of the external bus clock (CLKT). Set the
clock divide-by rate of the external extended bus interface clock (CLKT). The values written
to these bits determine the divide-by rate (clock frequency) of the external extended bus
interface clock in relation to the base clock, which can be selected from the 16 types shown
in Table 3.12-22.
Table 3.12-22 Clock Divide-By Rate (External Bus Clock) Settings
T3 T2 T1
0 0 0
0 0 0
0 0 1
0 0 1
0 1 0
0 1 0
0 1 1
0 1 1
... ... ...
1 1 1
Note: φ: Frequency of the system base clock
• These bits are readable and writable.
[bit3 to bit0] (Reserved)
These bits are reserved.
bit 15 14 13
T3 T2 T1
H
R/W R/W R/W
0 0 0
X X X
T0 Clock divide-by rate
φ
0
φ x 2 (divided by 2)
1
φ x 3 (divided by 3)
0
φ x 4 (divided by 4)
1
φ x 5 (divided by 5)
0
φ x 6 (divided by 6)
1
φ x 7 (divided by 7)
0
φ x 8 (divided by 8)
1
... ...
φ x 16 (divided by 16)
1
CHAPTER 3 CPU AND CONTROL UNITS
12 11 10 9
T0 - - -
R/W R/W R/W R/W
0 0 0 0
X X X X
Clock frequency: if the source oscillation is
17[MHz] and the PLL is multiplied by 4
68 [MHz] (initial value)
34 [MHz]
22.7 [MHz]
17 [MHz]
13.6 [MHz]
11.3 [MHz]
9.71 [MHz]
8.5 [MHz]
4.25 [MHz]
8
-
R/W
0
X
...
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