Fujitsu FR60 Hardware Manual page 139

[bit11] (Reserved)
This bit is reserved.
[bit10] PLL1EN (PLL1 ENable)
This bit is the enable bit of the main PLL.
Rewriting of this bit is disabled while the main PLL is selected as the clock source.
Selection of the main PLL as the clock source is disabled while this bit is set to "0" (because
of the setting of bit9 and bit8, which are the CLKS1 and CLK0 bits).
Table 3.12-17 Function of the main PLL operation enable bit (PLL1EN)
PLL1EN
0 Main PLL stopped (initial value)
1 Main PLL enabled
• This bit is initialized to "0" by a reset (INIT).
• This bit is readable and writable.
[bit9, bit8] CLKS1, CLKS0 (CLocK source Select)
These bits set the clock source that will be used by the MB91301 series.
The values written to these bits determine the clock source, which can be selected from the
two types shown in Table 3.12-18.
Table 3.12-18 Clock Source Settings
CLKS1 CLKS0
0 0
0 1
1 0
1 1
Table 3.12-19 shows the combinations of the CLKS1 and CLKS0 bits that cannot be changed
and those that can.
Table 3.12-19 Combinations of CLKS1 and CLKS0 Bits that Can and Cannot Be Changed
Cannot be changed
"00 " --> "11
B
"01 " --> "10
B
"10 " --> "01
B
"11 " --> "00
B
• These bits are initialized to "00
• These bits are readable and writable.
Source oscillation input from X0/X1 divided by 2 (initial value)
Source oscillation input from X0/X1 divided by 2
Main PLL
Do not make a setting
"
B
"
B
" or "11 "
B B
" or "10 "
B B
" by a reset (INIT).
B
CHAPTER 3 CPU AND CONTROL UNITS
Function
Clock source setting
Can be changed
"00 " --> "01 " or "10
B B
"01 " --> "11 " or "00
B B
"10 " --> "00
B
"11 " --> "01
B
"
B
"
B
"
B
"
B
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