Device States And State Transitions - Fujitsu FR60 Hardware Manual

3.13.1 Device States and State Transitions

This section describes device operating states and the transition between operating
states.
■ RUN State (Normal Operation)
In the RUN state, a program is being executed. All internal clocks are supplied and all circuits
are enabled.
For the 16-bit peripheral bus, however, only the bus clock is stopped, when it is not being
accessed.
In this state, a state transition request is accepted. If synchronous reset mode is selected,
however, state transition operations different from normal reset mode are used for some
requests. For more information, see "Synchronous Reset Operation" in Section "3.11.5 Reset
Operation Modes".
■ Sleep State
In the sleep state, a program is stopped. Program operation causes a transition to this state.
Only execution of the program on the CPU is stopped; peripheral circuits are enabled. The
instruction cache is stopped and the built-in memory modules and the internal and external
buses are stopped unless the DMA controller issues a request.
• If a valid interrupt request occurs, the state is cleared and the RUN state (normal operation)
is entered.
• If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)
state is entered.
• If an operation initialization reset (RST) request occurs, the operation initialization reset
(RST) state is entered.
■ Stop State
In the stop state, the device is stopped. Program operation causes a transition to this state.
All internal circuits are stopped. All internal clocks are stopped and the oscillation circuit and
PLL can be stopped if set to do so. Be sure to set PLL1EN=0 before entering the stop state.
In addition, the external pins (except some) can be set to high impedance via settings.
• If a specific valid interrupt request (no clock required) occurs, the oscillation stabilization wait
RUN state is entered.
• If a settings initialization reset (INIT) request occurs, the settings initialization reset (INIT)
state is entered.
• If an operation initialization reset (RST) request occurs, the oscillation stabilization wait reset
(RST) state is entered.
CHAPTER 3 CPU AND CONTROL UNITS
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