Pll Controls - Fujitsu FR60 Hardware Manual

CHAPTER 3 CPU AND CONTROL UNITS

3.12.1 PLL Controls

Operation (oscillation) enable and disable and the multiply-by rate setting can be
independently controlled for each of the PLL oscillation circuits corresponding to the
main source clock. Each control is set in the clock source control register (CLKR).
This section describes each control.
■ PLL Operation Enable
To enable or disable the main PLL oscillation, set bit10 (PLL1EN bit) of the clock source control
register (CLKR).
❍ PLL operation control
In self-induced oscillation mode, either the operation enable/disable bit or the multiply-by rate
setting bit is initialized to "0" after a settings initialization reset (INIT), causing the PLL oscillation
to stop. While it is stopped, PLL output cannot be selected as the source clock.
When the program operation starts, set the multiply-by rate of the PLL to be used as the clock
source, enable it, and switch the source clock after the PLL lock wait time elapses. For the PLL
lock wait time, use of a time-base timer interrupt is recommended.
While PLL output is selected as the source clock, the PLL cannot be stopped (writing to the
register is disabled). To stop a PLL upon transition to stop mode, reselect as the source clock
the main clock divided by two before stopping the PLL.
If bit0 (OSCD1 bit) of the standby control register (STCR) is set to stop oscillation in stop mode,
the corresponding PLL automatically stops when the device enters stop mode. As a result, you
do not need to set operation stop. When the device returns from stop mode later, the PLL
automatically restarts the oscillation operation. If oscillation is not set to stop in stop mode, the
PLL does not automatically stop. In this case, set operation stop before transition to stop mode
as required.
■ PLL Multiply-by Rate
Set the multiply-by rate of the main PLL in bit14 to bit12 (PLL1S2, PLL1S1, and PLL1S0 bits) of
the clock source control register (CLKR).
After a settings initialization reset (INIT), all bits are initialized to "0".
❍ PLL multiply-by rate setting in self-induced oscillation mode
To change the PLL multiply-by rate setting from the initial value in self-induced oscillation mode,
do so before or as soon as the PLL is enabled after the program has started execution. After
changing the multiply-by rate, switch the source clock after the lock wait time elapses. For the
PLL lock wait time, use of a time-base timer interrupt is recommended.
To change the PLL multiply-by rate setting during operation, switch the source clock to a clock
other than the PLL in question before making the change. After changing the multiply-by rate,
switch the source clock after the lock wait time has elapsed, as described above.
You can also change the PLL multiply-by rate setting while using a PLL. In this case, however,
the program stops running after the device automatically enters the oscillation stabilization wait
state after the multiply-by rate setting is rewritten and does not resume execution until the
specified oscillation stabilization wait time has elapsed.
The program does not stop running if the clock source is switched to a clock other than a PLL.
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