Fujitsu FR60 Hardware Manual page 237

• The access sequence when burst cycles are used can be divided into the following two
types:
- First access cycle
The first access cycle is the start cycle for the burst access and operates in the same way as
the normal single access cycle.
- Page access cycle
The page access cycle is a cycle following the first access cycle in which both CSn and RD
(read strobe) are asserted. Wait cycles that are different from those set for a single cycle can
be set. The page access cycle is repeated while access remains in the address boundary
determined by the burst length setting. When access within the address boundary ends,
burst access terminates and CSn is negated.
• Setting of the W15 to W12 bits of the AWR register enable the first 0 to 15 wait cycles to be
inserted. At this point, the minimum number of the first access cycles is the wait cycles + 2
cycles (three cycles in the timing chart shown in Figure 4.6-1).
• Setting of the W11 to W08 bits of the AWR register enables 0 to 15 page wait cycles to be
inserted. At this point, the page access cycles can be obtained from the page wait cycles + 1
cycle (Two cycles in the timing chart shown in Figure 4.6-1).
• Setting of the BST bits of the ACR register enables the burst length to be set as "1", "2", "4", or
"8". If the burst length is set to "1", single access mode is set and only the first cycle is
repeated. However, if the data bus width is set to 32 bits (the BST bits of the ACR register are
"10 "), set the burst length to "4" or less (A malfunction occurs if the burst length is set to "8").
B
• If burst access is enabled, burst access is used when prefetch access or transfer with a
larger size than the specified data bus width is performed. For example, if word access to an
area whose data bus width is set to 8 bits and burst length to "4" is performed, access of 4
bursts is performed once instead of repeating byte access four times.
• Since RDY input is ignored in areas for which burst access is set, do not set TYP3 to
TYP0=0xx1 .
B
• The LBA and BAA signals are designed for burst FLASH memory. LBA indicates the start of
access and BAA indicates the address increment.
• A31 to A00 is updated after the wait cycles that were set during burst access.
• For fly-by transfer, burst access operation cannot be performed.
CHAPTER 4 EXTERNAL BUS INTERFACE
217