Fujitsu FR60 Hardware Manual page 625

I
I Flag
I Flag ................................................................ 81
I/O Circuit Types
I/O Circuit Types ............................................... 26
I/O Map
I/O Map .......................................................... 536
I/O Pins
I/O Pins........................................................... 147
I/O Port
Basic Block Diagram of the I/O Port.................. 258
I/O Port Modes ................................................ 259
I/O Wait Registers
Configuration of the I/O Wait Registers for DMAC
(IOWR0,IOWR1) ............................... 170
Functions of Bits in the I/O Wait Registers for DMAC
(IOWR0,IOWR1) ............................... 170
2
I C
2
I C Bus Interface ................................................. 5
2
I C Bus Interface
2
I C Bus Interface ................................................. 5
2
I C Interface
2
I C Interface Registers...................................... 451
2
I C interface
Operational Explanation ................................... 468
IBCR
Bus Control Register (IBCR0/IBCR1) ............... 456
IBSR
Bus Status Register (IBSR0/IBSR1) .................. 454
ICCR
Clock Control Register (ICCR0/ICCR1) ............ 462
ICE
Configuration Example :Target Board + Evaluation
Chip + ICE ......................................... 534
ICHCR
Instruction Cache Control Register (ICHCR) ........ 54
ICR
Bit Configuration of Interrupt Control Register
(ICR) ................................................. 334
Configuration of Interrupt Control Register
(ICR) ................................................... 82
Detailed Bit of Interrupt Control Register
(ICR) ................................................. 334
Mapping of Interrupt Control Register (ICR) ........ 82
ICS
Input Capture Control Registers
(ICS01,ICS23) .................................... 493
IDAR
Data Register (IDAR0/IDAR1) ......................... 467
IDBL
Clock Disable Register (IDBL0/IDBL1) ............ 467
ILM
Interrupt Level Mask (ILM) Register ................... 81
Immediate Set
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions .........................................583
Immediate Transfer Instructions
Immediate Set/16-bit/32-bit Immediate Transfer
Instructions .........................................583
INIT
Setting Initialization Reset (INIT) Clear
Sequence ..............................................98
Settings Initialization Reset (INIT) .......................95
Settings Initialization Reset (INIT) State.............135
INIT
INIT Pin Input (Settings Initialization Reset
Pin) ......................................................96
Initial Value
Allocation of a Variable with an Initial Value......565
Initialization
Initialization.....................................................376
Reset (Device Initialization) ................................94
Initialization Reset
INIT Pin Input (Settings Initialization Reset
Pin) ......................................................96
Operation Initialization Reset (RST).....................95
Operation Initialization Reset (RST) Clear
Sequence ..............................................98
Operation Initialization Reset (RST) State...........134
Setting Initialization Reset (INIT) Clear
Sequence ..............................................98
Settings Initialization Reset (INIT) .......................95
Settings Initialization Reset (INIT) State.............135
Input Capture
Block Diagram of the Input Capture ...................492
Overview of Input Capture ................................490
Registers of the Input Capture............................491
Input Capture Control Registers
Input Capture Control Registers
(ICS01,ICS23).....................................493
Input Capture Data Registers
Input Capture Data Registers
(IPCP0 to IPCP3) ................................493
Instruction
How to Read the Instruction Lists ......................573
Instruction Format ............................................577
Operation of INT Instruction ...............................91
Operation of INTE Instruction .............................91
Operation of RETI Instruction .............................93
Operation of Undefined Instruction Exception .......92
Instruction Cache
Areas Cacheable by the Instruction Cache.............59
Configuration of Instruction Cache.......................51
Instruction Cache..................................................3
Instruction Cache Tags........................................52
Updating Entries in the Instruction Cache .............59
Instruction Cache Control Register
Instruction Cache Control Register (ICHCR).........54
INDEX
605