Fujitsu FR60 Hardware Manual page 622

INDEX
DEOP
Function of the DACK, DEOP,and DREQ Pins... 404
Timing of the DEOP Pin Output ........................ 431
Detection
0 Detection ...................................................... 447
0 Detection Data Register (BSD0) ..................... 445
1 Detection ...................................................... 447
1 Detection Data Register (BSD1) ..................... 445
Change Point Detection .................................... 448
Lack of Error Detection .................................... 570
Detection Result Register
Detection Result Register (BSRR) ..................... 446
Device
State of Device and Each Transition................... 132
Device Initialization
Reset (Device Initialization) ................................ 94
Device States
Device States ................................................... 131
DICR
Delayed Interrupt Control Register (DICR)......... 327
DLYI Bit of DICR............................................ 328
Dimensions
Dimensions.......................................................... 8
Direct Addressing
Direct Addressing Area....................................... 42
Direct Addressing Instructions
Direct Addressing Instructions........................... 595
Division
Clock Division ................................................. 108
DIVR
Base Clock Division Setting Register 0
(DIVR0) ............................................. 120
Base Clock Division Setting Register 1
(DIVR1) ............................................. 123
DLYI
DLYI Bit of DICR............................................ 328
DMA
Clearing Peripheral Interrupts by DMA .............. 422
DMA Access Operation .................................... 236
DMA Fly-By Transfer (I/O ->Memory).............. 237
DMA Fly-By Transfer
(I/O ->SDRAM/FCRAM) .................... 241
DMA Fly-By Transfer (Memory ->I/O).............. 239
DMA Fly-By Transfer
(SDRAM/FCRAM ->I/O) .................... 243
DMA Transfer and Interrupts ............................ 419
DMA Transfer during Sleep .............................. 425
DMA Transfer Request during External Hold ..... 420
External Hold Request during DMA Transfer ..... 420
Operation Timing for DMA Fly-By Transfer
(I/O ->Memory) .................................. 214
Operation Timing for DMA Fly-By Transfer
(Memory ->I/O) .................................. 215
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request............... 420
602
Suppressing DMA............................................ 419
DMA Access Operation
DMA Access Operation.................................... 236
DMA Controller
DMA Controller (DMAC) Registers .................. 386
DMAC (DMA Controller) .................................... 3
DMA External Interface
DMA External Interface Pins ............................ 438
DMA Transfer
DMA Transfer and Interrupts ............................ 419
DMA Transfer during Sleep.............................. 425
External Hold Request during DMA Transfer ..... 420
DMA Transfer Request
DMA Transfer Request during External Hold ..... 420
Simultaneous Occurrence of a DMA Transfer Request
and an External Hold Request .............. 420
DMAC
AC Characteristics of DMAC............................ 431
Configuration of the I/O Wait Registers for DMAC
(IOWR0,IOWR1) ............................... 170
DMA Controller (DMAC) Registers .................. 386
DMAC (DMA Controller) .................................... 3
Functions of Bits in the I/O Wait Registers for DMAC
(IOWR0,IOWR1) ............................... 170
DMAC All-Channel Control Register
Bit Configuration of DMAC All-Channel Control
Register (DMACR) ............................. 402
Detailed Bit of DMAC All-Channel Control Register
(DMACR) .......................................... 402
DMAC Interrupt Control
DMAC Interrupt Control .................................. 425
DMACA
Bit Configuration of Control/Status Registers A
(DMACA0 to DMACA4) .................... 388
Detailed Bit of Control/Status Registers A
(DMACA0 to DMACA4) .................... 388
DMACB
Bit Configuration of Control/Status Registers B
(DMACB0 to DMACB4)..................... 393
Detailed Bit of Control/Status Registers B
(DMACB0 to DMACB4)..................... 393
DMACR
Bit Configuration of DMAC All-Channel Control
Register (DMACR) ............................. 402
Detailed Bit of DMAC All-Channel Control Register
(DMACR) .......................................... 402
DMADA
Bit Configuration of Transfer Source/Transfer
Destination Address Setting Registers
(DMASA0 to DMASA4/DMADA0 to
DMADA4) ......................................... 400
Detailed Bit of Transfer Source/Transfer Destination
Address Setting Registers (DMASA0 to
DMASA4/DMADA0 to DMADA4) ..... 400