Dma Fly-By Transfer (I/O -> Sdram/Fcram) - Fujitsu FR60 Hardware Manual

4.10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)
This section describes the operation of DMA fly-by transfer (I/O device to SDRAM/
FCRAM).
■ DMA Fly-By Transfer (I/O -> SDRAM/FCRAM)
Figure 4.10-3 shows an operation timing chart assuming TYP3 to TYP0 set to 1000
to 0051
H
Figure 4.10-3 Timing Chart for DMA Fly-by Transfer (I/O to SDRAM/FCRAM)
MCLK
A31 to A00
AS
CSn
SRAS
SCAS
WRn(SWE)
D31 to D00
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic
mode
DEOPn
IORD
DREQn
, and IOWR set to 41 .
H
Basic cycle
CHAPTER 4 EXTERNAL BUS INTERFACE
I/O wait
I/O hold
cycle wait
memory
address
, AWR set
B
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