Fujitsu FR60 Hardware Manual page 608

APPENDIX E INSTRUCTION LISTS
■ Delayed Branch Instructions
Table E.2-12 Delayed Branch Instructions
Mnemonic Type
JMP:D @Ri
CALL:D label12
CALL:D @Ri
RET:D
BRA:D label9
BNO:D label9
BEQ:D label9
BNE:D label9
BC:D label9
BNC:D label9
BN:D label9
BP:D label9
BV:D label9
BNV:D label9
BLT:D label9
BGE:D label9
BLE:D label9
BGT:D label9
BLS:D label9
BHI:D label9
Notes:
• In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and
sets them as shown below:
(label12-PC-2)/2 --> rel11, (label9-PC-2)/2 --> rel8; label12 and label9 have a sign.
• A delayed branch always occurs after the next instruction (delay slot) is executed.
• Instructions that can be placed in the delay slot are all 1-cycle, a-, b-, c-, and d-cycle
instructions.
Multicycle instructions cannot be placed in the delay slot.
588
OP CYCLE
E 9F-0 1
F D8 1
E 9F-1 1
E 9F-2 1
D F0 1
D F1 1
D F2 1
D F3 1
D F4 1
D F5 1
D F6 1
D F7 1
D F8 1
D F9 1
D FA 1
D FB 1
D FC 1
D FD 1
D FE 1
D FF 1
NZVC Operation
---- Ri --> PC
---- PC+4 --> RP ,
PC+2+(label12-PC-2) --> PC
---- PC+4 --> RP ,Ri --> PC
---- RP --> PC
---- PC+2+(label9-PC-2) -->PC
---- No branch
---- if(Z==1) then
PC+2+(label9-PC-2) -->PC
---- s/Z==0
---- s/C==1
---- s/C==0
---- s/N==1
---- s/N==0
---- s/V==1
---- s/V==0
---- s/V xor N==1
---- s/V xor N==0
---- s/(V xor N) or Z==1
---- s/(V xor N) or Z==0
---- s/C or Z==1
---- s/C or Z==0
Remarks
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