Self Refresh - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.9.1

Self Refresh

This section describes self-refreshing.
■ Self Refresh
Writing "1" to the SELF bit in the refresh control register (RCR) causes the SDRAM/FCRAM
interface to initiate the self-refresh transition sequence.
After executing auto-refreshing the number of times set in the RFC2 to RFC0 bits, the SDRAM/
FCRAM interface issues the SELF command to SDRAM/FCRAM to enter the self-refresh mode.
The device is released from the self-refresh mode either when "0" is written to the SELF bit or
read/write access to SDRAM/FCRAM occurs.
The SDRAM/FCRAM interface issues the SELFX command to execute auto-refreshing the
number of times set in the RFC2 to RFC0 bits upon detection of writing "0" to the SELF bit or
access to SDRAM/FCRAM in the self-refresh mode.
Even when access to SDRAM/FCRAM by DMA transfer occurs after setting the self-refresh
mode and putting the chip into sleep mode, the self-refresh mode is canceled.
❍ Self-refresh mode transition procedure
1) Set SELF bit to "1".
2) Issue the REF command the number of times set in the RFC2 to RFC0 bits.
3) Issue SELF command
❍ Self-refresh mode reset procedure
1) Set the SELF bit to "0" or access to SDRAM/FCRAM.
2) Issue SELFX command
3) Issue the REF command the number of times set in the RFC2 to RFC0 bits.
4) Transition to the normal access state
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