Channel Selection And Control - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)

14.3.11 Channel Selection and Control

Up to five channels can be simultaneously set as transfer channels. In general, an
independent function can be set for each channel.
■ Priority among Channels
Since DMA transfer is possible only on one channel at a time, priority must be set for the
channels.
Two modes, fixed and rotation, are provided as the priority settings and can be selected for
each channel group (described later).
❍ Fixed mode
The order of priority is fixed by channel number, with priority ascending from channel 0 to
channel 4:
(ch.0 > ch.1 > ch.2 > ch.3 > ch.4)
If a transfer request with a higher priority is received during a transfer, the transfer channel
becomes the channel with the higher priority when the transfer for the transfer unit (number set
in the block size specification register x data width) ends.
When higher priority transfer is completed, transfer is restarted on the previous channel.
ch.0 transfer request
ch.1 transfer request
Bus operation
Transfer ch
ch.0 transfer end
ch.1 transfer end
❍ Rotation mode (between ch.0 and ch.1 only)
When operation is enabled, the initial states have the same order that they would have in fixed
mode, but at the end of each transfer operation, the priority of the channels is reversed. Thus, if
more than one transfer request is output at the same time, the channel is switched after each
transfer unit.
This mode is effective when continuous or burst transfer is set.
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Figure 14.3-4 Timing Example in Fixed Mode
CPU SA DA
ch.1
SA DA SA DA SA
ch.0 ch.0
DA CPU
ch.1