Input Timing Of The Dreqx Pin - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series

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14.6.1 Input Timing of the DREQx Pin

The DREQx pin is a DMA start request signal. If the pin is also used as a port, enable

the DREQ input using the PFR register. This section shows the input timing of the

■ Timing of Transfer other than Demand Transfer

For transfer other than demand transfer, set the DMA start source to edge detection. Although

there is no rule for rise/fall timing, use three or more clock cycles as the holding time the DREQ

signal. To make another transfer request, enter the request after the DMA transfer is completed

(make a request after DEOP is output).

If a request is made before DEOP is output, it may be ignored.

Figure 14.6-1 shows the timing chart for transfer other than demand transfer.

Figure 14.6-1 Timing Chart for Transfer other than the Demand Transfer

When a DREQx edge is requested (for 2-cycle transfer)

CPU operation

3 or more cycles

CHAPTER 14 DMA CONTROLLER (DMAC)

MAD transfer

The next request must be

after DEOP output