Table of Contents
Advertisement
1.4 Block Diagram
X0,X1
RSTX
MD2,1,0
FIP0/LED0
to
FIP16/LED16
FIP17 to FIP59
P90/SDA/SO3
P91/SCL/SC3
2
MB90M405 F
MC-16LX FAMILY HARDWARE MANUAL
CPU
Controller
Clock
controller
ROM
(96/128 KB)
RAM
(4 KB)
FL Controller
V-RAM
Serial I/O
(ch 3)
2
I
C Interface
Fig. 1.1 Block Diagram (MB90M405)
Timer clock
divider
8-/10-bit A/D
Converter
Serial I/O
(ch 2)
External interrupt
input controller
16-bit free-run timer
16-bit input capture
(ch 0, 1)
16-bit output
compare
16-bit reload timer
(ch 0, 1, 2)
UART
(ch.0,1)
1-6
PA0/AN0/TMCK
PA1/AN1
PA2/AN2
PA3/AN3
PA4/AN4
PA5/AN5
PA6/AN6
PA7/AN7
PB0/AN8
PB1/AN9
PB2/AN10
PB3/AN11/SI2
PB4/AN12/SC2/TIN
PB5/AN13/SO2/TO
PB6/AN14/INT3
PB7/AN15/INT2
P80/IC0/INT0
P81/IC1/INT1
P82/SI0
P83/SC0
P84/SO0
P85/SI1
P86/SI2
P87/SI3
Advertisement
Table of Contents
