Fujitsu FR60 Hardware Manual page 573

■ Pin State Table
Table C-1 Pin States in External Bus 32-Bit Mode (1 / 3)
Specified
Port
Pin no. function
name
name
1 to 5 P13 to P17 D11 to D15
8 to 15 P20 to P27 D16 to D23
18 to 25 - D24 to D31
28 P80 RDY
29 P81 BGRNT
30 P82 BRQ
31 P83 RD
DQMUU/
32 P84
WR0
DQMUL/
33 P85
WR1
DQMLU/
34 P86
WR2
DQMLL/
35 P87
WR3
36 P90 SYSCLK
37 P91 MCLKE
38 P92 MCLK
39 P93 -
SRAS/LBA/
40 P94
AS
41 P95 SCAS/BAA
42 P96 SWE/WR
At initialization (INIT)
Function
Function
name
name
Initial
value
Bus width Bus width
32 bits 8 bits
D11 to D15 P13 to P17
D16 to D23 P20 to P27
Output Hi-Z
Input ready
D24 to D31 D24 to D31
P80 P80
Output Hi-Z
P81 P81
Input ready
P82 P82
RD RD
"H" output
DQMUU/ DQMUU/
WR0 WR0
DQMUL/
P85
WR1
DQMLU/
P86 F : "H" output
WR2
DQMLL/
P87
WR3
Asserted :
"L" output
SYSCLK SYSCLK
Negated :
CLK output
MCLKE MCLKE "H" output F : "L" output F : "L" output
Asserted :
"L" output
MCLK MCLK
Negated :
CLK output
Output Hi-Z
P93 P93
Input ready
Output Hi-Z
P94 P94
Input ready
Output Hi-Z
P95 P95
Input ready
Output Hi-Z
P96 P96
Input ready
APPENDIX C PIN STATE IN EACH CPU STATE
Stop mode
Sleep
mode
HIZ=0 HIZ=1
P : Previous P : Previous
Output
state held state held
Hi-Z/
F : Output F : Output
input 0
held or held or
fixed
Hi-Z Hi-Z
P : Previous
state held
F : RDY
input
P : Previous
Previous
state held
state held
F : "H" output
P : Previous
state held
Output
F : BRQ in-
Hi-Z/input
put invalid
0 fixed
P : Previous
Previous
state held
state held
F : "H" output
P : Previous P : Previous Output
Hi-Z/
state held state held
F : SYSCLK F : "H" or "L"
input 0
output output fixed
F : Output
Hi-Z
P : Previous P : Previous
F : Output
state held state held
Hi-Z
F : "H" output F : "H" output
Previous Previous Output
state held state held Hi-Z
P : Previous
Output
"H" output
state held
Hi-Z
F : "H" output
P : Previous
Output
"H" output
state held
Hi-Z
F : "H" output
P : Previous Output
state held Previous Hi-Z/
F : SWEX state held
input 0
output
fixed
Bus open
(BGRNT)
CS CS not
shared shared
Output Output
Hi-Z Hi-Z
P : Previous P : Previous
state held state held
F : RDY F : RDY
input input
"L" output "L" output
BRQ input BRQ input
Previous Output
state held Hi-Z
F : CLK F : CLK
output output
Output
"H" output
Hi-Z
Output F : CLK
Hi-Z
output
Port Port
Output F :
Hi-Z
"H" output
Output
"H" output
Hi-Z
Output Previous
Hi-Z state held
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