Basic Timing - Fujitsu FR60 Hardware Manual

4.5.1

Basic Timing

This section shows the basic timing for successive accesses.
■ Basic Timing (For Successive Accesses)
Figure 4.5-1 shows the operation timing for (TYP3 to TYP0 = 0000
READ
WRITE
• AS is asserted for one cycle in the bus access start cycle.
• A31 to A00 continues to output the address of the location of the start byte in word/halfword/
byte access from the bus access start cycle to the bus access end cycle.
• If the W02 bit of the AWR0 to AWR7 registers is "0", CS0 to CS7 are asserted at the same
timing as AS. For successive accesses, CS0 to CS7 are not negated. If the W00 bit of the
AWR register is "0", CS0 to CS7 are negated after the bus cycle ends. If the W00 bit is "1",
CS0 to CS7 are negated one cycle after bus access ends.
• RD and WR0 to WR3 are asserted from the 2nd cycle of the bus access. Negation occurs
after the wait cycle of bits W15 to W12 of the AWR register is inserted. The timing of
asserting RD and WR0 to WR3 can be delayed by one cycle by setting the W01 bit of the
AWR register to "1".
• If a setting is made so that WR0 to WR3 is used like TYP3 to TYP0=0x0x
"H".
• For read access, D31 to D00 is read when MCLK rises in the cycle in which the wait cycle
ended after RD was asserted.
• For write access, data output to D31 to D00 starts at the timing at which WR0 to WR3 are
asserted.
Figure 4.5-1 Basic Timing (For Successive Accesses)
MCLK
A31 to A00
AS
CSn
RD
D31 to D00
WRn
D31 to D00
CHAPTER 4 EXTERNAL BUS INTERFACE
#1 #2
#1 #2
#1 #2
, AWR = 0008 ).
B H
, WRn is always
B
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