Fujitsu FR60 Hardware Manual page 476

2
CHAPTER 16 I C INTERFACE
• Writing "0" to the MSS bit during master interrupt: (MSS=1, INT=1: IBCR)
• Writing "1" to the SCC bit during master interrupt: (MSS=1, INT=1: IBCR)
• Clearing the INT bit
• Beginning of a transfer byte that is not used for the transfer target as master or slave
■ Bus Control Register (IBCR0/IBCR1)
Address: 000094
Bits other than BER and BEIE are cleared if the I
[bit15] BER (Bus Error)
This bit is the bus error interrupt request flag bit.
For a read by a read modify instruction, "1" is always read.
During writing
0
1
During reading
0
1
If this bit is set, the EN bit of the CCR register is cleared, stopping the I
halting data transfer. All bits of the IBSR and IBCR registers other than BER and BEIE are
cleared.
This bit must be cleared before the I
This bit is set to "1" if:
• An illegal START or STOP condition at a specific location is detected (while a slave
address or data is being transferred).*
• The header section of a slave address is received during a 10-bit read access before a
10-bit write access with the first byte is performed. *
• A STOP condition is detected in master mode.
*: While the I
[STOP] condition is received to prevent an illegal bus error report.
[bit14] BEIE (Bus Error Interrupt Enable)
This bit is the bus error interrupt enable bit.
0
1
An interrupt occurs if this bit is set to "1" and the BER bit is set to "1".
456
bit 15 14
/0000B4
BER BEIE
H H
R/W R/W
Initial value=> 0 0
Clears the bus error interrupt request flag.
Irrelevant
Bus error not detected
Error condition detected
2
C interface is enabled during transfer, this detection flag is set after the first
Bus error interrupt disabled
Bus error interrupt enabled
13 12 11
SCC MSS ACK GCAA
W R/W R/W R/W
0 0 0
2
C interface is stopped (EN=0: ICCR).
2
C interface is enabled (EN=1) again.
10 9 8
INTE INT
R/W R/W
0 0 0
2
C interface and