Fujitsu FR60 Hardware Manual page 75

The following describes the functions of the instruction cache control register (ICHCR) bits.
[bit7] RAM (RAM mode)
If this bit is "1", RAM mode is set.
In RAM mode, set the ENAB bit to "0" to turn off the instruction cache.
[bit5] GBLK (Global lock)
This bit locks all the current entries to the instruction cache. If a miss occurs when GBLK=1,
a valid entry in the instruction cache is not updated. However, invalid subblocks are updated.
The instruction data fetch operation at this time is the same as when the entries are not
locked.
[bit4] ALFL (Autolock fail)
This bit (ALFL) is set to "1" if locking is attempted on an entry that is already locked. If, during
entry autolock, an entry update is attempted on an entry that is already locked, no new entry
is locked in the instruction cache regardless of what the user intends. Reference this bit for
debugging of a program or similar purpose.
Clear this bit by writing "0" to it.
[bit3] EOLK (Entry autolock)
This bit either enables or disables an autolock setting on an entry in the instruction cache. An
entry accessed if this bit (EOLK) is "1" (only if a miss occurs) is locked when the hardware
sets the entry lock bit in the instruction cache tag to "1". After this point, a locked entry is not
subject to update when an instruction cache miss occurs. However, invalid subblocks are
updated. To ensure that an entry is locked, flush the cache and set this bit.
[bit2] ELKR (Entry lock clear)
This bit specifies clearing of the entry lock bit in all the instruction cache tags. In the cycle
following the one in which this bit (ELKR) is set to "1", the entry lock bit in all the cache tags
is cleared to "0". However, the content of this bit is held only for one clock cycle and the bit is
cleared to "0" in the second and later clock cycles.
[bit1] FLSH (Flash)
This bit specifies flushing of the instruction cache. Set this bit (FLSH) to "1" to flush the
instruction cache. However, the content of this bit is held only for one clock cycle and the bit
is cleared to "0" in the second and later clock cycles.
[bit0] ENAB (Enable)
This bit either enables or disables the instruction cache. If this bit (ENAB) is "0", the
instruction cache is disabled and an instruction access from the CPU becomes external
directly without going through the instruction cache. In the disabled state, the contents of the
instruction cache are maintained.
CHAPTER 3 CPU AND CONTROL UNITS
55