Fujitsu FR60 Hardware Manual page 462

CHAPTER 14 DMA CONTROLLER (DMAC)
❍ Fly-by transfer mode
Figure 14.6-4 shows the timing chart in fly-by transfer mode.
RD
DQMUU/DQMUL
WR/WRn
IORD
IOWR
DACK (AKxx=111
DACK (AKxx=001
DACK (AKxx=010
DACK (AKxx=011
DACK (AKxx=100
DACK (AKxx=101
DACK (AKxx=110
* : AKxx is the setting value in the PFR register that corresponds to the DMA channel.
442
Figure 14.6-4 Timing Chart in Fly-By Transfer Mode
*
)
B
*
)
B
*
) Fly-by transfer setting disabled
B
*
) Fly-by transfer setting disabled
B
) * Fly-by transfer setting disabled
B
) * Fly-by transfer setting disabled
B
*
) Fly-by transfer setting disabled
B
Memory to I/O
Same timing as the chip select
I/O to memory Memory to I/O I/O to memory