Block Diagram Of Clock Generation Section - Fujitsu MB90335 Series Hardware Manual

CHAPTER 5 CLOCK

5.2 Block Diagram of Clock Generation Section

5.2 Block Diagram of Clock Generation Section
The clock generation section consists of the following five blocks:
• System clock generation circuit
• PLL multiplying circuit
• Clock selector
• Clock select register (CKSCR)
• Oscillation stabilization wait time selector
■ Block Diagram of Clock Generation Section
Figure 5.2-1 shows the block diagram of the clock generation section.
Figure 5.2-1 contains the standby control and time-base timer circuits.
RST Pin
Reset (Cancellation)
Interrupt (Cancellation)
Clock
generation
unit
Pin
X0
X1
Pin
126
Figure 5.2-1 Block Diagram of Clock Generation Section
Low power consumption mode control register (LPMCR)
STP SLP SPL RST TMD
2
Operation
clock
selector
PLL frequency
MCM
multiplication circuit RESERVED
Clock selection register (CKSCR)
2
-division
Oscillation clock
(HCLK)
System clock
generation circuit
FUJITSU MICROELECTRONICS LIMITED
CG1 CG0
Reserved
CPU intermittent
operation sector
Standby
control circuit
WS1 WS0 MCS CS1 CS0
RESERVED
512 4 2
-division -division -division
Main
clock
Time-base timer
MB90335 Series
Pin high
Pin high
impedance
impedance
control circuit
control
Internal reset
generation Internal reset
circuit
Intermittent cycle
selection
CPU clock
CPU clock
control circuit
Stop, Sleep signal
Stop signal
Peripheral
Oscillation stable
clock
wait cancellation
control circuit
Main clock oscillation stabilization wait cancellation
Machine
clock
Oscillation
stable wait
2
time
selector
2
2 2 2
-division -division -division -division
to Watchdog timer
2 4
-division
CM44-10137-6E