CHAPTER 4 EXTERNAL BUS INTERFACE
4.1
Overview of the External Bus Interface
This section explains the features, block diagram, I/O pins, and registers of the
external bus interface.
■ Features
The external bus interface has the following features:
❍ Addresses of up to 32 bits (4 Gbytes space) can be output.
❍ Various kinds of external memory (8-bit/16-bit/32-bit modules) can be directly connected
and multiple access timings can be mixed and controlled.
•
Asynchronous SRAM and asynchronous ROM/FLASH memory (multiple write strobe method
or byte enable method)
•
Page mode ROM/FLASH memory (Page sizes 2, 4, and 8 can be used)
•
Burst mode ROM/FLASH memory
•
SDRAM (FCRAM modules are also supported, including two- and four-bank types with CAS
latency 1 to 8)
•
Address/data multiplex bus (8-bit/16-bit width only)
•
Synchronous memory (such as ASIC built-in memory) (Synchronous SRAM cannot be
directly connected)
❍ Eight independent banks (chip select areas) can be set, and chip select corresponding to
each bank can be output.
•
The size of each area can be set in multiples of 64K bytes (64K bytes to 2G bytes for each
chip select area).
•
An area can be set at any location in the logical address space (Boundaries may be limited
depending on the size of the area.)
❍ In each chip select area, the following functions can be set independently:
•
Enabling and disabling of the chip select area (Disabled areas cannot be accessed)
•
Setting of the access timing type to support various kinds of memory (SDRAM can be
connected to the CS6 and CS7 areas only.)
•
Detailed access timing setting (individual setting of the access type such as the wait cycle)
•
Setting of the data bus width (8-bit/16-bit/32-bit)
•
Setting of the order of bytes (big endian or little endian) (Only big endian can be set for the
CS0 area)
•
Setting of write disable (read-only area)
•
Enabling and disabling of fetches from the built-in cache
•
Enabling and disabling of the prefetch function
•
Maximum burst length setting (1, 2, 4, 8)
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