Transfer Sequence - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)

14.3.2 Transfer Sequence

The transfer type and the transfer mode that determine, for example, the operation
sequence after DMA transfer has started can be set independently for each channel
(Settings for TYPE[1:0] and MOD[1:0] of DMACB).
■ Selection of the Transfer Sequence
The following sequence can be selected with a register setting:
• Burst 2-cycle transfer
• Demand 2-cycle transfer
• Block/step 2-cycle transfer
• Burst fly-by transfer
• Demand fly-by transfer
• Block/step fly-by transfer
❍ Burst 2-cycle transfer
In a burst 2-cycle transfer, as many transfers as specified by the transfer count are performed
continuously for one transfer source. For a 2-cycle transfer, all 32-bit areas can be specified
using a transfer source/transfer destination address.
A peripheral transfer request, software transfer request, or external pin (DREQ) edge input
detection request can be selected as the transfer source.
Table 14.3-1 shows the specifiable transfer addresses (burst 2-cycle transfer).
Table 14.3-1 Specifiable Transfer Addresses (Burst 2-cycle Transfer)
Transfer source addressing
All 32-bit areas specifiable
The following are some features of a burst transfer:
When one transfer request is received, transfer is performed continuously until the transfer
count register reaches 0.
The transfer count is the transfer count x block size (BLK[3:0] of DMACA x DTC[15:0] of
DMACA).
Another request occurring during transfer is ignored.
If the reload function of the transfer count register is enabled, the next request is accepted after
transfer ends.
If a transfer request for another channel with a higher priority is received during transfer, the
channel is switched at the boundary of the block transfer unit. Processing resumes only after the
transfer request for the other channel is cleared.
410
Direction Transfer destination addressing
→
All 32-bit areas specifiable