Fujitsu FR60 Hardware Manual page 331

[bit3] UNDR (UNDeR flow flag): Indicates generating underflow
This bit indicates that an underflow has occurred.
If the UNDR bit is set while the UTIE bit of bit4 is set to "1", an underflow interrupt occurs.
The UNDR bit is cleared upon a reset or if "0" is written to it.
For a read by a read-modify-write instruction, "1" is always read.
Writing "1" to the UNDR has no effect.
[bit2] CLKS (clock select): Cascade specification
This bit is the cascade specification bit for ch.0 and ch.1 of the U-TIMER.
Table 8.2-3 Cascade specification
CLKS
0 Uses a peripheral clock (φ) as the clock source. [initial value]
1 Uses an underflow signal of Channel 0 as the U-TIMER source clock timing. *
*: f.f. shown in the block diagram
CLKS is valid only for ch.1 and ch.2. This bit must always be set to "0" for Channel 0.
φ (Peripheral clock = CLKP) has a different cycle depending on the gear setting.
[bit1] UTST (U-TIMER STart): Operation enable
This bit is the U-TIMER operation enable bit.
Table 8.2-4 Operation Enable
UTST
Stopped. Writing "0" during operation stops running of the U-TIMER. [initial
0
value]
1 Operated. Writing "1" during operation does not stop the U-TIMER.
[bit0] UTCR (U-TIMER CleaR)
Writing "0" to UTCR clears the U-TIMER to 0000
The read value is always "1".
CHAPTER 8 U-TIMER
Operation
Operation
(also clears the f.f. to "0").
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