Clock Generation Control - Fujitsu FR60 Hardware Manual

3.12 Clock Generation Control

This section describes clock generation and control.
■ Clock Generation Control
The internal operating clock of the FR family device is generated as follows:
• Selection of a source clock:
• Generation of a base clock:
• Generation of an internal clock:Divide the base clock and generate three types of operating
The following section describes the generation and control of each clock. For detailed
information about the registers and flags described below, see "3.12.5 Block Diagram of Clock
Generation Controller" and "3.12.6 Register of Clock Generation Controller".
The symbol "φ", which is shown in Table 3.12-4, Table 3.12-9, Table 3.12-13, Table 3.12-16,
Table 3.12-20, Table 3.12-21 and Table 3.12-22, indicates the basic clock that is achieved by
dividing the source clock by two or performing PLL oscillation. Therefore, the system base clock
is the clock which is generated where the above base clock is generated.
■ Source Clock
❍ Self-induced oscillation mode (X0/X1 pin input)
In this mode, an oscillator is connected to external oscillation pins and the original oscillation
generated by the built-in oscillation circuit is used as the source clock.
The source for supply of all clocks, including the external bus clock, is the MB91301 series
itself.
The main clock, generated from the X0/X1 pins, is intended to be used as a high-speed clock.
The main clock is multiplied by the built-in main PLL, each of which can be independently
controlled.
Generate an internal base clock by selecting one of the following source clocks:
• Main clock divided by 2
• Main clock multiplied in the main PLL
Select a source clock by setting the clock source control register (CLKR).
CHAPTER 3 CPU AND CONTROL UNITS
Select a clock supply source.
Divide the source clock by two or perform PLL oscillation to
generate a base clock.
clocks, which are supplied to each section.
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