Fujitsu FR60 Hardware Manual page 506

CHAPTER 17 16-BIT FREE RUN TIMER
Figure 17.5-2 Clearing the Counter when the Counter Value Matches that of the Compare Clear Register
Counter value
FFFF
BFFF
7FFF
3FFF
0000
H
Reset
Compare register
Interrupt
❍ Timing to Clear the 16-bit Free Run Timer
The counter is cleared by reset, software, or when the counter value matches that of the
compare clear register. When clearing the counter by way of reset or software, it is cleared
immediately when a clear command is issued. However, when the counter is cleared because
of a match with the value in the compare clear register 0, clearing is performed in
synchronization with the count timing.
φ
Compare clear register value
Counter clear
Counter value
❍ Count Timing of the 16-bit Free Run Timer
The 16-bit free run timer is incremented by the input clock (internal or external clock). When an
external clock is selected, the falling edge (indicated by a down arrow) of the external clock is
synchronized with the system clock, then the 16-bit free run timer counts up at the falling edge
of the internal count clock.
φ
External clock input
Internal count clock
Counter value
486
H
H
H
H
BFFF
H
Figure 17.5-3 Clear Timing of the Free Run Timer
Figure 17.5-4 Count Timing of the 16-bit Free Run Timer
Match
N
N
N + 1
Match
Time
0 0 0 0
H