Fujitsu FR60 Hardware Manual page 307

[bit13] MDSE: Mode selection bit
This bit determines whether the PPG operation in which pulses are generated continuously
or the one-shot operation in which only single pulses are generated is used.
Table 7.3-2 Mode selection setting
MDSE
0
1
[bit12] RTRG: Restart enable bit
This bit determines whether restart through a software trigger or trigger input is allowed.
Table 7.3-3 Restart enable setting
RTRG
0
1
[bit11, bit10] CKS1, CKS0: Counter clock selection bit
These bits select the counter clock of the 16-bit down counter.
Table 7.3-4 Counter clock selection setting
CKS1
0
0
1
1
φ: Peripheral machine clock
[bit9] PGMS: PPG output mask selection bit
When this bit is written to "1", the PPG output can be masked to "0" or "1" regardless of the
mode setting, cycle setting, or duty ratio setting.
PPG output when PGMS is set to "1" is shown below.
Table 7.3-5 PPG Output when PGMS is Set to "1"
Polarity
Normal polarity
Reverse polarity
For output of all-"H" for normal polarity (or all-"L" for reverse polarity), write the same value to
the cycle set register and the duty set register to obtain the reverse output of these mask
values.
PPG operation (initial value)
One-shot operation
Restart disabled (initial value)
Restart enabled
CKS0
0
1
0
1
CHAPTER 7 PPG TIMER
Function
Function
Cycle
φ (initial value)
φ/4
φ/16
φ/64
PPG output
"L" output
"H" output
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