Fujitsu FR60 Hardware Manual page 140

CHAPTER 3 CPU AND CONTROL UNITS
■ Base Clock Division Setting Register 0 (DIVR0)
Figure 3.12-7 shows the configuration of the Base Clock Division Setting Register 0 (DIVR0)
bits.
Figure 3.12-7 Configuration of Base Clock Division Setting Register 0 (DIVR0) Bits
Address: 000486
Initial value (INIT)
Initial value (RST)
Base Clock Division Setting Register 0 (DIVR0) controls the divide-by rate of an internal clock in
relation to the base clock. This register sets the divide-by rates of the CPU clock, the clocks of
an internal bus (CLKB) and a peripheral circuit, and the peripheral bus clock (CLKP).
An upper-limit frequency for the operation is set for each clock. If you set a combination of
source clock, PLL multiply-by rate setting, and divide-by rate setting that results in a frequency
exceeding this upper-limit frequency, operation is not guaranteed. Be extra careful of the order
in which you change settings to select the source clock and to configure the associated setting
items.
If the setting in this register is changed, the new divide-by rate takes effect for the clock rate
following the one in which the setting was made.
120
bit 15 14 13
B3 B2 B1
H
R/W R/W R/W
0 0 0
X X X
12 11 10 9
B0 P3 P2 P1
R/W R/W R/W R/W
0 0 0 1
X X X X
8
P0
R/W
1
X