Burst Access Operation - Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series

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CHAPTER 4 EXTERNAL BUS INTERFACE

Burst Access Operation

In the external bus interface, the operation that transfers successive data items in one

access sequence is called burst access. The normal access cycle (that is, not burst

access) is called single access. One access sequence starts with an assertion of AS

and CSn and ends with negation of CSn. Multiple data items two or more units of data

of the unit set for the area.

This section explains burst access operation.

■ Burst Access Operation

Figure 4.6-1 shows the operation timing chart for (first wait cycle=1, inpage access wait cycle=1,

TYP3 to TYP0=0000

• In the external bus interface, the operation that transfers successive data items in one

access sequence is called burst access. The normal access cycle (that is, not burst access)

is called single access. One access sequence starts with an assertion of AS and CSn and

ends with negation of CSn. Multiple data items two or more units of data of the unit set for

In addition to more efficient use of access cycles when a sizable amount of data of

asynchronous memory such as page mode ROM and burst flash memory is read, burst

cycles can also be used for reading from normal asynchronous memory.

Figure 4.6-1 Timing Chart for Burst Access