Fujitsu FR60 Hardware Manual page 113

■ No-coprocessor Trap
If a coprocessor instruction using a coprocessor that is not installed is executed, a no-
coprocessor trap occurs.
[Operation]
1) (TBR+3E0
2) SSP-4 --> SSP
3) PS --> (SSP)
4) SSP-4 --> SSP
5) Address of next instruction --> (SSP)
6) "0" --> S flag
7) TMP --> PC
■ Coprocessor Error Trap
If an error occurs while a coprocessor is being used and then a coprocessor instruction that
operates on the coprocessor is executed, a coprocessor error trap occurs.
[Operation]
1) (TBR+3DC
2) SSP-4 --> SSP
3) PS --> (SSP)
4) SSP-4 --> SSP
5) Address of next instruction --> (SSP)
6) "0" --> S flag
7) TMP --> PC
■ Operation of RETI Instruction
The RETI instruction specifies return from the EIT processing routine.
[Operation]
1) (R15) --> PC
2) R15+4 --> R15
3) (R15) --> PS
4) R15+4 --> R15
The RETI instruction must be executed while the S flag is set to "0".
■ Precaution on Delay Slot
A delay slot for a branch instruction has restrictions regarding EIT.
See Section "3.9 Branch Instructions".
) --> TMP
H
) --> TMP
H
CHAPTER 3 CPU AND CONTROL UNITS
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