Fujitsu FR60 Hardware Manual page 55

❍ D-bus memory
Do not set a code area in D-bus memory.
No instruction fetch is performed to the D-bus.
Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can
cause the microcontroller to lose control.
Do not set a data area in I-bus memory.
❍ I-bus memory
Do not set a stack area or vector table in I-bus memory.
It may cause a hang during EIT processing (including RETI).
Recovery from the hang requires a reset.
Do not perform DMA transfer to I-bus memory.
❍ Notes on the PS register
Since some instructions manipulate the PS register earlier, the following exceptions may cause
the interrupt handler to break or the PS flag to update its display setting when the debugger is
being used. As the microcontroller is designed to carry out reprocessing correctly upon
returning from such an EIT event, it performs operations before and after the EIT as specified in
either case.
• The following operations may be performed when the instruction immediately followed by a
DIV0U/DIV0S instruction is (a) halted by a user interrupt or NMI, (b) single-stepped, or (c)
breaks in response to a data event or emulator menu:
1. D0 and D1 flags are updated earlier.
2. The EIT handler (user interrupt/NMI or emulator) is executed.
3. Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1
flags are updated to the same values as those in (1) above.
• The following operations are performed when the OR CCR/ST ILM/MOV Ri and PS instructions
are executed to enable interruptions when a user interrupt or NMI trigger event has occurred.
1. The PS register is updated earlier.
2. The EIT handler (user interrupt/NMI) is executed.
3. Upon returning from the EIT, the above instructions are executed and the PS register is
updated to the same value as that in (1) above.
❍ R15 (General purpose register)
When any of the following instructions is executed, the SSP* or USP* value is not used as R15,
resulting in an incorrect value written to memory.
AND R15, @Ri
OR R15, @Ri
EOR R15, @Ri
XCHB @Rj, R15
* : R15 is a virtual register. When a program attempts to access R15, the SSP or USP is
accessed depending on the status of the "S" flag as an SP flag. When coding the above ten
instructions using an assembler, specify a general-purpose register other than R15.
CHAPTER 2 HANDLING THE DEVICE
ANDH R15, @Ri
ORH R15, @Ri
EORH R15, @Ri
ANDB R15, @Ri
ORB R15, @Ri
EORB R15, @Ri
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