Fujitsu FR60 Hardware Manual page 177

32-bit microcontroller mb91301 series
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❍ CS area mask setting function
If you want to set an area some of whose operation settings are changed for a certain CS area
(referred to as the base setting area), you can set TYPE3 to TYPE0 of ARC in another CS area
to "1111
" so that the area can function as a mask setting area.
B
If you do not use the mask setting function, disable any overlapping area settings for multiple
CS areas.
Access operations to the mask setting area are as follows:
CSn corresponding to a mask setting area is not asserted.
CSn corresponding to a base setting area is asserted.
For the following ACR settings, the settings on the mask setting area side are valid:
bit11, bit10 (DBW1, DBW0): Bus width setting
bit9, bit8 (BST1, BST0):
bit7 (SREN):
bit6 (PFEN):
bit5 (WREN):
bit4 (LEND):
For the following ACR setting, the setting on the base setting area side is valid:
bit3 to bit0 (TYPE3 to TYPE0): Access type setting
For the AWR settings, the settings on the mask setting area side are valid.
For the CHER settings, the settings on the mask setting area side are valid.
A mask setting area can be set for only part of another CS area (base setting area). You cannot
set a mask setting area for an area without a base setting area. In addition, the mask setting
area must not be duplicated. Use care when setting ASR and bits ASZ3 to ASZ0 of ACR.
The following restrictions apply when using these bits:
A write-enable setting cannot be implemented by a mask.
Write-enable settings in the base CS area and the mask setting area must be identical.
If write operations to a mask setting area are disabled, the area is not masked and operates
as a base CS area.
If write operations to the base CS area are disabled but are enabled to the mask setting
area, the area has no base, resulting in malfunctions.
CHAPTER 4 EXTERNAL BUS INTERFACE
Burst length setting
Sharing-enable setting
Prefetch-enable setting
Write-enable setting (For this setting only, only a setting that
is the same as that of the base setting area is allowed)
Little endian setting
157

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