Fujitsu FR60 Hardware Manual page 602

APPENDIX E INSTRUCTION LISTS
■ Multiply Instructions
Table E.2-5 Multiply Instructions
Mnemonic
MUL Rj,Ri
MULU Rj,Ri
MULH Rj,Ri
MULUH Rj,Ri
DIV0S Ri
DIV0U Ri
DIV1 Ri
DIV2 Ri
DIV3
DIV4S
*1
DIV Ri
*2
DIVU Ri
*1: DIV0S, DIV1 x 32, DIV2, DIV3, or DIV4S is generated. The instruction code length becomes 72 bytes.
*2: DIV0U or DIV1 x 32 is generated. The instruction code length becomes 66 bytes.
582
Type OP CYCLE
A AF 5
A AB 5
A BF 3
A BB 3
E 97-4 1
E 97-5 1
E 97-6 d
E 97-7 1
E 9F-6 1
E 9F-7 1
36
33
NZVC Operation
Ri × Rj --> MDH,MDL
CCC-
Ri × Rj --> MDH,MDL
CCC-
Ri × Rj --> MDL
CC--
Ri × Rj --> MDL
CC--
----
----
-C-C
-C-C
----
----
-C-C MDL / Ri --> MDL,
MDL % Ri --> MDH
-C-C MDL / Ri --> MDL,
MDL % Ri --> MDH
Remarks
32bits × 32bits=64bits
No sign
16bits × 16bits=32bits
No sign
Step operation
32bits/32bits=32bits