Fujitsu FR60 Hardware Manual page 396

CHAPTER 13 UART
■ Initialization
The following shows the setting values of the control registers required to use CLK synchronous
mode.
• SMR register
• MD1, MD0:"10
• CS:
• SCKE:
• SOE:
• SCR register
• PEN:
• P,SBL,A/D: These bits are meaningless.
• CL:
• REC:
• RXE, TXE: At least one of the bits must be set to "1".
• SSR register
• RIE: Set to "1" to enable interrupts and to "0" to disables interrupts.
• TIE: "0"
■ Start of Communication
Write to the SODR register to start communication.
If only reception is performed, dummy send data must be written to the SODR register.
■ End of Communication
Check for the end of communication by making sure that the RDRF flag of the SSR register has
changed to "1". Use the ORE bit of the SSR register to check that communication has been
performed correctly.
376
"
B
Specifies the clock input.
Set to "1" for an internal timer and to "0" for an external clock.
Set to "1" for send and to "0" for receive.
"0"
"1"
"0" (to initialize the register)