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Fujitsu FR60 Hardware Manual

32-bit microcontroller mb91301 series.
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FUJITSU SEMICONDUCTOR
CM71-10114-4E
CONTROLLER MANUAL
FR60
32-BIT MICROCONTROLLER
MB91301 Series
HARDWARE MANUAL

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   Summary of Contents for Fujitsu FR60

  • Page 1

    FUJITSU SEMICONDUCTOR CM71-10114-4E CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91301 Series HARDWARE MANUAL...

  • Page 3

    Be sure to refer to the “Check Sheet” for the latest cautions on development. “Check Sheet” is seen at the following support page URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html “Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system development.

  • Page 5

    DVD players, that require a high level of CPU processing power. The MB91301 series is one of the FR60 of microcontrollers, which are based on the FR30/40 of CPUs. It has enhanced bus access and is optimized for high-speed use.

  • Page 6

    ■ Structure of This Manual This manual consists of the following 20 chapters and an appendix. CHAPTER 1 OVERVIEW This chapter provides basic information required to understand the MB91301 series, and covers features, a block diagram, and functions. CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling the MB91301 series.

  • Page 7

    CHAPTER 14 DMA CONTROLLER (DMAC) This chapter describes the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation. CHAPTER 15 BIT SEARCH MODULE This chapter describes the bit search module, the configuration and functions of registers, and bit search module operation. CHAPTER 16 I C INTERFACE This chapter describes the bit search module, the configuration and functions of registers,...

  • Page 8

    Fujitsu does not warrant proper operation of the device with respect to use based on such information. When you develop equipment incorporating the device based on such information, you must assume any responsibility arising out of such use of the information. Fujitsu assumes no liability for any damages whatsoever arising out of the use of the information.

  • Page 9

    How to Read This Manual ■ Terms Used in This Manual The following defines principal terms used in this manual. Term Meaning I-bus 32 bit bus for internal instructions. In the FR family, which is based on an internal Harvard architecture, independent buses are used for instructions and data. A bus converter is connected to the I-bus.

  • Page 11: Table Of Contents

    CONTENTS CHAPTER 1 OVERVIEW ....................1 Features of the MB91301 Series ......................2 Block Diagram ............................ 7 Package Dimensions .......................... 8 Pin Layout ............................11 Pin No. Table ............................ 13 List of Pin Functions ......................... 15 I/O Circuit Types ..........................26 CHAPTER 2 HANDLING THE DEVICE ................

  • Page 12

    3.12 Clock Generation Control ....................... 103 3.12.1 PLL Controls ..........................104 3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time ............ 105 3.12.3 Clock Distribution ........................106 3.12.4 Clock Division ..........................108 3.12.5 Block Diagram of Clock Generation Controller ................109 3.12.6 Register of Clock Generation Controller ..................

  • Page 13

    SDRAM/FCRAM Interface Operation ..................... 224 4.9.1 Self Refresh ..........................228 4.9.2 Power-on Sequence ........................229 4.9.3 Connecting SDRAM/FCRAM to Many Areas ................230 4.9.4 Address Multiplexing Format ..................... 231 4.9.5 Memory Connection Example ....................232 4.10 DMA Access Operation ........................236 4.10.1 DMA Fly-By Transfer (I/O ->...

  • Page 14

    Activating Multiple Channels by Using the General Control Register ..........303 Notes on Use of the PPG Timer ..................... 305 CHAPTER 8 U-TIMER ....................307 Overview of the U-TIMER ....................... 308 U-TIMER Registers ......................... 309 U-TIMER Operation ........................313 CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER .......

  • Page 15

    13.3.2 CLK Synchronous Mode ......................375 13.3.3 Occurrence of Interrupts and Timing for Setting Flags .............. 377 13.4 Example of Using the UART ......................380 13.5 Example of Setting Baud Rates and U-TIMER Reload Values ............382 CHAPTER 14 DMA CONTROLLER (DMAC) ..............383 14.1 Overview of the DMA Controller (DMAC) ..................

  • Page 16

    CHAPTER 17 16-BIT FREE RUN TIMER ............... 477 17.1 Overview of 16-bit Free Run Timer ....................478 17.2 Registers of the 16-bit Free Run Timer ..................479 17.3 Block Diagram of the 16-bit Free Run Timer .................. 480 17.4 Details on Registers of the 16-bit Free Run Timer ................. 481 17.5 Operation of the 16-bit Free Run Timer ..................

  • Page 17

    Main changes in this edition Page Changes (For details, refer to main body.) Part number is deleted. (MB91301, MB91V301) Table is changed in ■ Features of the MB91301 Series. (MB91301 is changed.) MB91301 and MB91V301are deleted in ■ Product Line-up is changed. Figure 1.2-1 Block Diagram is changed.

  • Page 18

    Page Changes (For details, refer to main body.) ■ Clock Generation Control is changed. (The followings sentences are added. The following section describes the generation and control of each clock. For detailed information about the registers and flags described below, see "3.12.5 Block Diagram of Clock Generation Controller"...

  • Page 19

    Page Changes (For details, refer to main body.) ■ Operation Timing of the WRn + Byte Control Type is changed. (• For write access, data output to D31-16 starts at the timing at which WRn is asserted. → • For write access, data output to D31 to D00 starts at the timing at which WR0 is asserted.) ■...

  • Page 20

    Page Changes (For details, refer to main body.) "Figure 13.2-1 Configuration of UART Registers" and "Figure 13.2-2 UART Registers" are changed. (DRCL is deleted.) (372) 13.2.5 DRCL Register is deleted. Figure 14.1-1 Block Diagram of the DMA Controller (DMAC) is changed. (DSAD 2-stage register →...

  • Page 21: Chapter 1 Overview

    CHAPTER 1 OVERVIEW This chapter provides basic information required to understand the MB91301 series, and covers features, a block diagram, and functions. 1.1 Features of the MB91301 Series 1.2 Block Diagram 1.3 Package Dimensions 1.4 Pin Layout 1.5 Pin No. Table 1.6 List of Pin Functions 1.7 I/O Circuit Types...

  • Page 22: Features Of The Mb91301 Series

    4-Kbyte RAM to increase the speed at which the CPU executes instructions. This model is an FR60 model that is based on the FR30/40 of CPUs. It has enhanced bus access and is optimized for high-speed use.

  • Page 23

    CHAPTER 1 OVERVIEW ■ Bus Interface • Maximum operating frequency of 68 MHz (at using SDRAM) • 24-bit address can be fully output (16-Mbyte space) • 8-bit, 16-bit and 32-bit data I/O • Prefetch buffer installed • Unused data and address pins can be used as general-purpose I/O ports. •...

  • Page 24

    CHAPTER 1 OVERVIEW • Internal peripheral can be selected at each channel as the transfer factor • Addressing mode with 32-bit full address specifications (increase, decrease, fixed) • Transfer modes (demand transfer, burst transfer, step transfer, block transfer) • Fly-by transfer supported (three channels between external I/O and external memory) •...

  • Page 25

    CHAPTER 1 OVERVIEW ■ I C Bus Interface • 2-channel master/slave transmission and reception of I C bus interface • Arbitration function and clock synchronization function of I C bus interface ■ Free Run Timer • 16-bit 1channel • Input capture 4 channels ■...

  • Page 26

    Currently in production Currently available *1: The Fujitsu product of real time OS REALOS/FR by conforming to the µITRON 3.0 is stored and optimized with the MB91302A. For details of built-in service call type and the specification of user task, see "CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE"...

  • Page 27: Block Diagram

    CHAPTER 1 OVERVIEW Block Diagram Figure 1.2-1 are the block diagram of the MB91301 series. ■ Block Diagram Figure 1.2-1 Block Diagram FR CPU I-Cache 4K bytes Core DREQ0,DREQ1 DACK0, DACK1 DMAC 5 ch DEOP0, DEOP1 Bit search IOWR IORD MB91302A : RAM 4K bytes MB91V301A...

  • Page 28: Package Dimensions

    +.007 .018 –.002 38.10±0.51 1.27±0.25 (1.500±.020) (.050±.010) +0.41 6.10(.240) 3.40 –0.36 +.016 .134 –.014 Dimensions in mm (inches). Note: The values in parentheses are reference values. 1994 FUJITSU LIMITED R179004SC-3-2 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...

  • Page 29

    (Stand off) (.024±.006) 0.25(.010) 0.40(.016) +0.05 0.18±0.035 0.145 –0.03 0.07(.003) .007±.001 +.002 .006 –.001 Dimensions in mm (inches). 2003 FUJITSU LIMITED F144024S-c-3-3 Note: The values in parentheses are reference values. Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...

  • Page 30

    (Stand off) 0.25(.010) 0.50±0.20 "A" (.020±.008) 0.60±0.15 LEAD No. (.024±.006) 0.50(.020) 0.22±0.05 0.08(.003) (.009±.002) Dimensions in mm (inches). Note: The values in parentheses are reference values. 2003 FUJITSU LIMITED F144019S-c-4-6 Please confirm the latest Package dimension by following URL. http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html...

  • Page 31: Pin Layout

    CHAPTER 1 OVERVIEW Pin Layout This section shows the pin layout of the MB91V301A, MB91302A. ■ Pin Layout of the MB91V301A Figure 1.4-1 is a diagram of the pin layout of the MB91V301A. Figure 1.4-1 Pin Layout of the MB91V301A INDEX 178 174 172 168 165 161 160 156 155 151 150 145 142 140...

  • Page 32

    CHAPTER 1 OVERVIEW ■ Pin Layout of the MB91302A Figure 1.4-2 is a diagram of the pin layout of the MB91302A. Figure 1.4-2 Pin Layout of the MB91302A P13/D11 DEOP1/PPG1/PB5 P14/D12 DACK1/TRG1/PB4 P15/D13 DREQ1/PB3 P16/D14 DEOP0/PB2 P17/D15 DACK0/PB1 DREQ0/PB0 P20/D16 P21/D17 TIN2/TRG3/PH2 P22/D18...

  • Page 33: Pin No. Table

    CHAPTER 1 OVERVIEW Pin No. Table The pin No. table of the MB91V301A is shown. ■ Pin No. Table Table 1.5-1 MB91V301A Pin No. Table (Package: PGA-179C-A03) (1 / 2) Pin Name Pin Name Pin Name N.C. P13/D11 P80/RDY P81/BGRNT P14/D12 P82/BRQ P15/D13...

  • Page 34

    CHAPTER 1 OVERVIEW Table 1.5-1 MB91V301A Pin No. Table (Package: PGA-179C-A03) (2 / 2) Pin Name Pin Name Pin Name ICD2 SOT0/PJ1 ICD1 SCK0/PJ2 INIT ICD0 SIN1/PJ3 SOT1/PJ4 SCK1/PJ5 BREAK PPG0/PJ6 CS0/PA0 ICLK TRG0/PJ7 CS1/PA1 ICS2 TIN0/PH0 CS2/PA2 ICS1 TIN1/PPG3/PH1 CS3/PA3 ICS0 TIN2/TRG3/PH2...

  • Page 35: List Of Pin Functions

    CHAPTER 1 OVERVIEW List of Pin Functions This section describes the pin functions of the MB91V301A, MB91302A. ■ Description of Pin Functions Table 1.6-1 lists the pin of the MB91V301A, MB91302A and their functions. Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (1 / 10) Pin no.

  • Page 36

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (2 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A External bus write strobe output. The pin has this WR1/ function when WR1 output is enabled. When WR1 DQMUL is used as the write strobe, this becomes the byte- enable pin (ULB).

  • Page 37

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (3 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A Address strobe output. The pin has this function without EDRAM area, when ASXE bit of port function register 9 is enabled.

  • Page 38

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (4 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A Data I/O pin for I C bus. This function is enable when typical operation of I C is enable.

  • Page 39

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (5 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A External interrupt inputs. These inputs are used continuously when the corresponding external INT0 to interrupt is enabled.

  • Page 40

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (6 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A External interrupt input. This input is used continuously when the corresponding external interrupt is enabled.

  • Page 41

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (7 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A External trigger input for PPG timer. This input is used continuously when the corresponding timer TRG0 input is enabled.

  • Page 42

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (8 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A External input for DMA transfer requests. This input is used continuously when external input for DMA transfer request is enabled.

  • Page 43

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (9 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A Chip select 0 output. The pin has this function when CS0 area of CSER (Chip Select Enable Register) is enabled and the specified CS0XE bit of port function register is enabled.

  • Page 44

    CHAPTER 1 OVERVIEW Table 1.6-1 List of Pin Function (except for Power Supply, and GND Pins) (10 / 10) Pin no. Pin name O circuit type Function MB91302A MB91V301A Chip select 6 output. The pin has this function when CS6 area of CSER is enabled and the specified CS6XE bit of port function register is enabled.

  • Page 45

    CHAPTER 1 OVERVIEW Table 1.6-3 Tool Pins Pin no. Pin name I/O circuit type Function MB91302A MB91V301A ICLK Clock output TRST Tool reset 98 to 100 ICS2 to ICS0 Device status output (during TRC) DSU4 operation status output (during EML) 90 to 93 ICD3 to ICD0 Trace information output (during...

  • Page 46: I/o Circuit Types

    CHAPTER 1 OVERVIEW I/O Circuit Types This section describes the I/O circuit types. ■ I/O Circuit Types Table 1.7-1 I/O Circuit Types (1 / 4) Type Circuit Remarks Oscillation feedback resistance approx. 1 MΩ Clock input P-ch N-ch Standby control CMOS hysteresis input with pull-up resistor Pull-up resistor value = approx.

  • Page 47

    CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (2 / 4) Type Circuit Remarks Analog input with switch P-ch N-ch P-ch Analog input N-ch Channel control CMOS level output without standby control P-ch N-ch Digital input CMOS level I/O with standby control Pull-up control and Pull-up control Pull-up resistor value = approx.

  • Page 48

    CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (3 / 4) Type Circuit Remarks CMOS level output Pull-up control CMOS level hysteresis input with Pull-up control Digital output P-ch P-ch no standby control Pull-up resistor value = approx. 25 kΩ Digital output N-ch (Typ)

  • Page 49

    CHAPTER 1 OVERVIEW Table 1.7-1 I/O Circuit Types (4 / 4) Type Circuit Remarks I/O buffer with pull-down CMOS level output P-ch = 4 mA Digital output Pull-up resistor value = approx. 25 kΩ N-ch (Typ) Digital output N-ch Digital input I/O buffer CMOS level output = 4 mA...

  • Page 50

    CHAPTER 1 OVERVIEW...

  • Page 51: Chapter 2 Handling The Device

    CHAPTER 2 HANDLING THE DEVICE This chapter provides precautions on handling the MB91301 series. 2.1 Precautions on Handling the Device 2.2 Precautions on Handling Power Supplies...

  • Page 52: Precautions On Handling The Device

    CHAPTER 2 HANDLING THE DEVICE Precautions on Handling the Device This section contains information on preventing a latch up and on the handling of pins. ■ Preventing a Latch Up A latch up can occur if, on a CMOS IC, a voltage higher than V or a voltage lower than V applied to an input or output pin or a voltage higher than the rating is applied between V and V...

  • Page 53

    On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.

  • Page 54

    CHAPTER 2 HANDLING THE DEVICE ❍ Low-power consumption mode (1) Be sure to use the following sequences after using the synchronous standby mode (TBCR: Set by time base counter control register bit8 SYNCS bit) when putting in the standby mode. /* Write to STCR */ #_STCR, r0 ;...

  • Page 55

    CHAPTER 2 HANDLING THE DEVICE ❍ D-bus memory Do not set a code area in D-bus memory. No instruction fetch is performed to the D-bus. Instruction fetches to the D-bus area result in incorrect data interpreted as code, which can cause the microcontroller to lose control.

  • Page 56

    CHAPTER 2 HANDLING THE DEVICE ❍ RETI instruction Do not neither control register of the instruction cache nor the data access to RAM of the instruction cache immediately before the instruction of RETI. ❍ Watchdog timer function The watchdog timer function of this model monitors whether a program holds over a reset within a specified time.

  • Page 57

    CHAPTER 2 HANDLING THE DEVICE ❍ ICE startup sequence When using the ICE, when you start debugging, ensure that the bus configuration is set correctly for the area being used before downloading. After turning on the power to the target, the states of the RD and WR0 to WR3 pins are undefined until you perform the above setting.

  • Page 58

    CHAPTER 2 HANDLING THE DEVICE ❍ Configuration batch file The example batch file below sets the mode vector and sets up the CS0 configuration register for the download area. Use values appropriate to the hardware in the wait, timing, and other settings.

  • Page 59: Precautions On Handling Power Supplies

    CHAPTER 2 HANDLING THE DEVICE Precautions on Handling Power Supplies This section provides precautions on power supplies with regard to pin handling and processing when power is turned on. ■ Processing after Power-on Immediately after power-on, be sure to apply a reset that initializes settings (INIT) from the INIT pin.

  • Page 60

    CHAPTER 2 HANDLING THE DEVICE...

  • Page 61: Chapter 3 Cpu And Control Units

    CHAPTER 3 CPU AND CONTROL UNITS This chapter provides basic information required to understand the functions of the FR family. It covers architecture, specifications, and instructions. 3.1 Memory Space 3.2 Internal Architecture 3.3 Instruction Cache 3.4 Dedicated Registers 3.5 General-Purpose Registers 3.6 Data Structure 3.7 Word Alignment 3.8 Memory Map...

  • Page 62: Memory Space

    CHAPTER 3 CPU AND CONTROL UNITS Memory Space The FR family has a logical address space of 4 G bytes (2 addresses), which the CPU accesses linearly. ■ Direct Addressing Area The areas in the address space listed below are used for input-output. These areas are called the direct addressing area.

  • Page 63

    CHAPTER 3 CPU AND CONTROL UNITS ■ Memory Map Figure 3.1-1 shows the memory map of the MB91301 series. Figure 3.1-1 Memory Map (MB91302A) (MB91302A) (MB91 V301A) (MB91302A) (MB91V301A) Internal ROM External ROM External ROM (Single chip Internal ROM External bus External bus External bus mode mode)

  • Page 64

    CHAPTER 3 CPU AND CONTROL UNITS Note: Each mode is set depending on the mode vector fetch after INIT is negated. (For mode setting, see “■MODE SETTINGS”.)

  • Page 65: Internal Architecture

    CHAPTER 3 CPU AND CONTROL UNITS Internal Architecture The FR family CPU is a high-performance core based on RISC architecture and advanced instructions for embedded applications. ■ Features ❍ RISC architecture used Basic instruction: One instruction per cycle ❍ 32-bit architecture General-purpose register: 32 bits x 16 ❍...

  • Page 66

    CPU and peripheral resources. A Harvard/Princeton bus converter is connected to both the I-bus and D-bus, providing an interface between the CUP and bus controllers. Figure 3.2-1 shows connections in the internal architecture. Figure 3.2-1 Internal Architecture FR60 CPU D-bus I-bus I address External address...

  • Page 67

    CHAPTER 3 CPU AND CONTROL UNITS ❍ CPU The CPU is a compact implementation of the 32-bit RISC FR family architecture. Five instruction pipe lines are used to execute one instruction per cycle. A pipeline consists of the following stages: •...

  • Page 68

    CHAPTER 3 CPU AND CONTROL UNITS ■ Overview of Instructions The FR family supports the general RISC instructions as well as logical operation, bit manipulation, and direct addressing instructions optimized for embedded applications. Each instruction is 16 bits long (some instructions 32 and 48 bits long), resulting in superior efficiency of memory use.

  • Page 69

    CHAPTER 3 CPU AND CONTROL UNITS ❍ Direct addressing Direct addressing instructions are used for access between an I/O and a general-purpose register or between an I/O and the memory. High-speed and high-efficiency access can be achieved since an I/O address is directly specified in an instruction instead of using register indirect addressing.

  • Page 70: Instruction Cache

    CHAPTER 3 CPU AND CONTROL UNITS Instruction Cache This section describes the instruction cache in detail. ■ Overview The instruction cache is temporary storage memory. When low-speed external memory accesses an instruction code, the instruction cache internally stores the code already accessed once time to increase the access speed for subsequent uses.

  • Page 71: Configuration Of The Instruction Cache

    CHAPTER 3 CPU AND CONTROL UNITS 3.3.1 Configuration of the Instruction Cache This section describes the configuration of the instruction cache. ■ Overview of Specifications The following is an overview of the instruction cache specifications: • FR family basic instruction length: 2 bytes •...

  • Page 72

    CHAPTER 3 CPU AND CONTROL UNITS ■ Instruction Cache Tags Figure 3.3-2 shows the configuration of the instruction cache tags. Figure 3.3-2 Configuration of Instruction Cache Tags Way 1 Address tag Blank SBV3 SBV2 SBV1 SBV0 TAGV Empty LRU ETLK Way 2 Address tag Empty...

  • Page 73

    CHAPTER 3 CPU AND CONTROL UNITS [bit0] ETLK (Entry lock) Locks into the cache all the entries in the block corresponding to the tag. The entries are locked if ETLK=1 (there is no updating) if a cache miss occurs. However, invalid sub blocks are updated.

  • Page 74: Configuration Of The Control Registers

    CHAPTER 3 CPU AND CONTROL UNITS 3.3.2 Configuration of the Control Registers Control registers include the cache size register (ISIZE) and the instruction cache register (ICHCR). This section describes the functions of these registers. ■ Configuration of Cache Size Register (ISIZE) Figure 3.3-3 shows the configuration of the cache size register (ISIZE) bits.

  • Page 75

    CHAPTER 3 CPU AND CONTROL UNITS The following describes the functions of the instruction cache control register (ICHCR) bits. [bit7] RAM (RAM mode) If this bit is "1", RAM mode is set. In RAM mode, set the ENAB bit to "0" to turn off the instruction cache. [bit5] GBLK (Global lock) This bit locks all the current entries to the instruction cache.

  • Page 76

    CHAPTER 3 CPU AND CONTROL UNITS Figure 3.3-5 Address Map of RAM Cache Cache Cache Cache Cache Cache off Cache 1 Kbyte Cache 2 Kbytes 4 Kbytes 4 Kbytes 2 Kbytes RAM on Address RAM off RAM on RAM on RAM off RAM on RAM off...

  • Page 77

    CHAPTER 3 CPU AND CONTROL UNITS Figure 3.3-7 Cache Area ROMA=0 ROMA=1 Address (No ROM) (ROM) 00000000 Direct area Direct area 00010000 IRAM IRAM 00020000 (Even in a D-bus RAM area cache 00030000 areas are cached through the IA bus.) 00040000 Internal ROM Each chip-select area can be...

  • Page 78: Instruction Cache Statuses And Settings

    CHAPTER 3 CPU AND CONTROL UNITS 3.3.3 Instruction Cache Statuses and Settings This section describes the state of the instruction cache in each operating modes and how to set up the instruction cache. ■ Instruction Cache Status in Each Operating Mode Table 3.3-2 shows the state of the instruction cache in each operating mode.

  • Page 79

    CHAPTER 3 CPU AND CONTROL UNITS ■ Updating Entries in the Instruction Cache Entries in the instruction cache are updated as shown in Table 3.3-3. Table 3.3-3 Updating of Entries in the Instruction Cache Unlock Lock Not updated Not updated Loads the memory and updates the Not updated for a tag miss.

  • Page 80: Setting Up The Instruction Cache Before Use

    CHAPTER 3 CPU AND CONTROL UNITS 3.3.4 Setting up the Instruction Cache before Use This section describes how to set up the instruction cache before it is used. ■ Setup Procedure Before using the instruction cache, set it up as follows: ❍...

  • Page 81

    CHAPTER 3 CPU AND CONTROL UNITS ❍ Disabling the instruction cache (OFF) To disable the instruction cache, set the ENAB bit to "0". #0x000003E7, r0 // I-Cache control register address #0B00000000, r1 // ENAB bit (Bit 0) r1, @r0 // Write to the register In this state maintained (which is the same as after reset), the instruction cache virtually does not exist and thus does nothing.

  • Page 82

    CHAPTER 3 CPU AND CONTROL UNITS ❍ Locking a specific instruction to the instruction cache To lock a specific group of instructions (subroutines, etc.) to the instruction cache, set the EOLK bit to "1" before executing the instructions. A locked instruction is accessed as if it is in high- speed internal ROM.

  • Page 83: Dedicated Registers

    CHAPTER 3 CPU AND CONTROL UNITS Dedicated Registers Use the dedicated registers for specific purposes. A program counter (PC), program status (PS), table base register (TBR), return pointer (RP), system stack pointer (SSP), user stack pointer (USP), and multiply and divide registers (MDH/MDL) are provided. ■...

  • Page 84

    CHAPTER 3 CPU AND CONTROL UNITS ■ Table Base Register (TBR) This section describes the functions of the table base register (TBR: Table Base Register). The table base register (TBR) consists of 32 bits. Figure 3.4-3 shows the configuration of table base register (TBR) bit.

  • Page 85

    CHAPTER 3 CPU AND CONTROL UNITS ■ User Stack Pointer (USP) This section describes the functions of the user stack pointer (USP: User Stack Pointer). The user stack pointer (USP) consists of 32 bits. Figure 3.4-6 shows the configuration of user stack pointer (USP) bit.

  • Page 86: Program Status (ps) Register

    CHAPTER 3 CPU AND CONTROL UNITS 3.4.1 Program Status (PS) Register The program status register (PS: Program Status) holds the program status. The PS register consists of three parts: ILM, SCR, and CCR. All undefined bits are reserved. During reading, 0 is always read. Writing is disabled. ■...

  • Page 87

    CHAPTER 3 CPU AND CONTROL UNITS [bit4] I (Interrupt enable flag) This bit enables or disables a user interrupt request. Table 3.4-2 shows the settings of this bit. Table 3.4-2 Functions of Interrupt Enable Flag (I) Value Description User interrupts disabled. When the INT instruction is executed, this bit is cleared to "0".

  • Page 88

    CHAPTER 3 CPU AND CONTROL UNITS [bit0] C (Carry flag) This bit indicates whether a carry or a borrow has occurred from the highest bit in the operation. Table 3.4-6 shows the settings of this bit. Table 3.4-6 Functions of Carry Flag (C) Value Description Indicates that no carry and borrow have occurred.

  • Page 89

    CHAPTER 3 CPU AND CONTROL UNITS [bit8] T (Step trace trap flag) This bit specifies whether the step trace trap is to be enabled. Table 3.4-7 shows the settings of this bit. Table 3.4-7 Functions of Step Trace Trap Flag (T) Value Description The step trace trap is disabled.

  • Page 90: General-purpose Registers

    CHAPTER 3 CPU AND CONTROL UNITS General-Purpose Registers Registers R0 to R15 are general-purpose registers. These registers are used as an accumulator in an operation or a pointer in a memory access. ■ General-purpose Registers Figure 3.5-1 shows the configuration of the general-purpose registers. Figure 3.5-1 Configuration of General-purpose Registers 32 bits [Initial value]...

  • Page 91: Data Structure

    CHAPTER 3 CPU AND CONTROL UNITS Data Structure The FR family uses the following two data ordering methods: • Bit ordering • Byte ordering ■ Bit Ordering The FR family uses the little endian method for bit ordering. Figure 3.6-1 shows the bit configuration in bit ordering. Figure 3.6-1 Bit Configuration in Bit Ordering bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ■...

  • Page 92: Word Alignment

    CHAPTER 3 CPU AND CONTROL UNITS Word Alignment Since instructions and data are accessed in byte units, the addresses at which they are placed depend on the instruction length or the data width. ■ Program Access A program for the FR family must be placed at an address that is a multiple of "2". Bit0 of the program counter (PC) is set to "0"...

  • Page 93: Memory Map

    CHAPTER 3 CPU AND CONTROL UNITS Memory Map This section shows the memory map for the FR family. ■ Memory Map The address space of memory is 32 bits linear. Figure 3.8-1 shows the memory map. Figure 3.8-1 Memory Map 0000 0000 Byte data 0000 0100...

  • Page 94: Branch Instructions

    CHAPTER 3 CPU AND CONTROL UNITS Branch Instructions An operation with or without a delay slot can be specified for a branch instruction used in the FR family. ■ Branch Instructions with Delay Slot Instructions written as follows perform a branch operation with a delay slot: JMP:D CALL:D label12...

  • Page 95: Operation Of Branch Instructions With Delay Slot

    CHAPTER 3 CPU AND CONTROL UNITS 3.9.1 Operation of Branch Instructions with Delay Slot In operation with a delay slot, the instruction located just after a branch instruction (placed in a "delay slot") is executed before the instruction that branches is executed. ■...

  • Page 96

    CHAPTER 3 CPU AND CONTROL UNITS ❍ RET:D instruction RP referenced by the RET:D instruction is not affected even though RP is updated by the instruction in the delay slot. [Example] RET:D Branch to address defined beforehand in RP No effect on the return operation ❍...

  • Page 97

    CHAPTER 3 CPU AND CONTROL UNITS ■ Limitations on Branch Instruction with Delay Slot ❍ Instructions that can be placed in the delay slot Only an instruction meeting the following conditions can be executed in the delay slot. • One-cycle instruction •...

  • Page 98: Operation Of Branch Instruction Without Delay Slot

    CHAPTER 3 CPU AND CONTROL UNITS 3.9.2 Operation of Branch Instruction without Delay Slot In operation without a delay slot, instructions are executed in the order in which they are specified. An instruction immediately following a branch is never executed before ■...

  • Page 99: Eit (exception, Interrupt, And Trap)

    CHAPTER 3 CPU AND CONTROL UNITS 3.10 EIT (Exception, Interrupt, and Trap) EIT, a generic term for exception, interrupt, and trap, refers to suspending program execution if an event occurs during execution and then executing another program. ■ EIT (Exception, Interrupt, and Trap) An exception is an event that occurs related to the execution context.

  • Page 100: Eit Interrupt Levels

    CHAPTER 3 CPU AND CONTROL UNITS 3.10.1 EIT Interrupt Levels The interrupt levels are 0 to 31 and are managed with five bits. ■ EIT Interrupt Levels Table 3.10-1 shows the allocation of the levels. Table 3.10-1 EIT Interrupt Levels Level Interrupt source Note...

  • Page 101

    CHAPTER 3 CPU AND CONTROL UNITS ■ I Flag A flag that specifies whether an interrupt is permitted or prohibited. This flag is provided as bit4 of the PS register. Table 3.10-2 shows the functions of I flag. Table 3.10-2 Functions of I Flag Value Description Interrupts prohibited...

  • Page 102: Interrupt Control Register (icr)

    CHAPTER 3 CPU AND CONTROL UNITS 3.10.2 Interrupt Control Register (ICR) The interrupt control register (ICR: Interrupt Control Register), located in the interrupt controller, sets the level of an interrupt request. An ICR is provided for each of the interrupt request inputs. The ICR is mapped on the I/O space and is accessed from the CPU through a bus.

  • Page 103: System Stack Pointer (ssp)

    CHAPTER 3 CPU AND CONTROL UNITS 3.10.3 System Stack Pointer (SSP) The system stack pointer (SSP) is used to point to the stack to save and restore data when EIT is accepted or a return operation occurs. ■ System Stack Pointer (SSP) The system stack pointer (SSP: System Stack Pointer) consists of 32 bits.

  • Page 104: Table Base Register (tbr)

    CHAPTER 3 CPU AND CONTROL UNITS 3.10.4 Table Base Register (TBR) The table base register (TBR: Table Base Register) indicates the beginning address of the vector table for EIT. ■ Table Base Register (TBR) The table base register (TBR) consists of 32 bits. Figure 3.10-4 shows the configuration of table base register (TBR) bits.

  • Page 105

    CHAPTER 3 CPU AND CONTROL UNITS Table 3.10-4 shows the vector table on the architecture. Table 3.10-4 Vector Table (1 / 3) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal Reset 000FFFFC Mode vector 000FFFF8 Reserved for system 000FFFF4 Reserved for system 000FFFF0...

  • Page 106

    CHAPTER 3 CPU AND CONTROL UNITS Table 3.10-4 Vector Table (2 / 3) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal UART2 (reception completed) ICR13 000FFF88 UART0 (transmission completed) ICR14 000FFF84 UART1 (transmission completed) ICR15 000FFF80 UART2 (transmission completed) ICR16 000FFF7C...

  • Page 107

    CHAPTER 3 CPU AND CONTROL UNITS Table 3.10-4 Vector Table (3 / 3) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal Reserved for system ICR44 000FFF0C Reserved for system ICR45 000FFF08 Reserved for system ICR46 000FFF04 Delayed interrupt source bit ICR47 000FFF00...

  • Page 108: Multiple Eit Processing

    CHAPTER 3 CPU AND CONTROL UNITS 3.10.5 Multiple EIT Processing If multiple EIT causes occur at the same time, the CPU repeats the operation of selecting and accepting one of the EIT causes, executing the EIT sequence, and then detecting EIT causes again. If there are no more EIT causes be accepted while the CPU is detecting EIT causes, the CPU executes the handler instruction of the last accepted EIT cause.

  • Page 109

    CHAPTER 3 CPU AND CONTROL UNITS In consideration of masking other causes after an EIT cause is accepted, the handlers of EIT causes that occur at the same time are executed in the order shown in Table 3.10-6. Table 3.10-6 Order of Executing EIT Handlers Order of executing Cause handlers...

  • Page 110: Eit Operations

    CHAPTER 3 CPU AND CONTROL UNITS 3.10.6 EIT Operations This section describes EIT operations. ■ EIT Operations In the following, it is assumed that the destination source PC indicates the address of the instruction that detected an EIT cause. In addition, "address of the next instruction" means that the instruction that detected EIT is as follows: •...

  • Page 111

    CHAPTER 3 CPU AND CONTROL UNITS A new EIT is detected before the execution of the first instruction in the handler, once the interrupt sequence is completed. If an acceptable EIT has occurred at this point, the CPU enters the EIT processing sequence. An instruction such as ORCCR, STILM, MOV Ri and PS may be executed twice before and after the interrupt handler, if it is executed to enable an interrupt while a user interrupt or NMI source is occurring.

  • Page 112

    CHAPTER 3 CPU AND CONTROL UNITS ■ Operation of Step Trace Trap Set the T flag in the SCR of the PS to enable the step trace function. A trap and a break then occur every time an instruction is executed. A step trace trap is detected under the following conditions: [Conditions of step trace trap detection] •...

  • Page 113

    CHAPTER 3 CPU AND CONTROL UNITS ■ No-coprocessor Trap If a coprocessor instruction using a coprocessor that is not installed is executed, a no- coprocessor trap occurs. [Operation] 1) (TBR+3E0 ) --> TMP 2) SSP-4 --> SSP 3) PS --> (SSP) 4) SSP-4 -->...

  • Page 114: Reset (device Initialization)

    CHAPTER 3 CPU AND CONTROL UNITS 3.11 Reset (Device Initialization) This section describes a reset (that is, device initialization) of the FR family. ■ Reset (Device Initialization) If a reset source occurs, the device stops all the programs and hardware operations and completely initializes the state.

  • Page 115: Reset Levels

    CHAPTER 3 CPU AND CONTROL UNITS 3.11.1 Reset Levels The reset operations of the FR family device are classified into two levels, each of which has different causes and initialization operations. This section describes these reset levels. ■ Settings Initialization Reset (INIT) The highest-level reset, which initializes all settings, is called a settings initialization reset (INIT).

  • Page 116: Reset Sources

    CHAPTER 3 CPU AND CONTROL UNITS 3.11.2 Reset Sources This section describes the reset sources and the reset levels in the FR family device. To determine reset sources that have occurred in the past, read the RSRR (reset source register). For more information about registers and flags described in this section, see Section "3.12.5 Block Diagram of Clock Generation Controller"...

  • Page 117

    CHAPTER 3 CPU AND CONTROL UNITS ■ Watchdog Reset Writing to the watchdog timer control register (RSRR) starts the watchdog timer. Unless A5 is written to the timebase counter clear register (CTBR) within the cycle specified in bit9 and bit8 (WT1 and WT0 bits) in the RSRR, a watchdog reset request occurs. A watchdog reset request is a settings initialization reset (INIT) request.

  • Page 118: Reset Sequence

    CHAPTER 3 CPU AND CONTROL UNITS 3.11.3 Reset Sequence When a reset source no longer exists, the device starts to execute the reset sequence. A reset sequence has different operations depending on the reset level. This section describes the operations of the reset sequence for different reset levels. ■...

  • Page 119: Oscillation Stabilization Wait Time

    CHAPTER 3 CPU AND CONTROL UNITS 3.11.4 Oscillation Stabilization Wait Time If a device returns from the state in which the original oscillation was or may have been stopped, the device automatically enters the oscillation stabilization wait state. This function prevents the use of oscillator output after starting before oscillation has stabilized.

  • Page 120

    CHAPTER 3 CPU AND CONTROL UNITS ■ Selecting an Oscillation Stabilization Wait Time The oscillation stabilization wait time is measured with the built-in time base counter. If a source for an oscillation stabilization wait occurs and the device enters the oscillation stabilization wait state, the built-in time base counter is initialized and then it starts to measure the oscillation stabilization wait time.

  • Page 121: Reset Operation Modes

    CHAPTER 3 CPU AND CONTROL UNITS 3.11.5 Reset Operation Modes Two modes for an operation initialization reset (RST) are provided: normal (asynchronous) reset mode and synchronous reset mode. The operation initialization reset mode is selected with bit7 (SYNCR bit) of the time base counter control register (TBCR).

  • Page 122

    CHAPTER 3 CPU AND CONTROL UNITS Reference: The DMA controller, which stops transfer when a request is accepted, does not delay transition to another state. If bit7 (SYNCR bit) of the time base counter control register (TBCR) is set to "1", synchronous reset mode is selected.

  • Page 123: Clock Generation Control

    CHAPTER 3 CPU AND CONTROL UNITS 3.12 Clock Generation Control This section describes clock generation and control. ■ Clock Generation Control The internal operating clock of the FR family device is generated as follows: • Selection of a source clock: Select a clock supply source.

  • Page 124: Pll Controls

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.1 PLL Controls Operation (oscillation) enable and disable and the multiply-by rate setting can be independently controlled for each of the PLL oscillation circuits corresponding to the main source clock. Each control is set in the clock source control register (CLKR). This section describes each control.

  • Page 125: Oscillation Stabilization Wait Time And Pll Lock Wait Time

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.2 Oscillation Stabilization Wait Time and PLL Lock Wait Time If a clock selected as the source clock is not already stabilized, an oscillation stabilization wait time is required (See Section "3.11.4 Oscillation Stabilization Wait Time").

  • Page 126: Clock Distribution

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.3 Clock Distribution An operating clock for each function is generated based on the base clock generated from the source clock. A total of four internal operating clocks are provided. A divide- by rate can be set independently for each of them. This section describes these internal operating clocks.

  • Page 127

    CHAPTER 3 CPU AND CONTROL UNITS ■ External Bus Clock (CLKT) This clock is used for external extended bus interfaces. It is used by the following circuits: • External extended bus interface • External CLK output • Bus interface port Since 68 MHz is the upper-limit frequency for operation, do not set a combination of multiply-by rate and divide-by rate that results in a frequency exceeding this limit.

  • Page 128: Clock Division

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.4 Clock Division A divide-by rate can be set independently for each of the internal operating clocks. With this function, an optimum operating frequency can be set for each circuit. ■ Clock Division Set a divide-by rate in Basic Clock Division Setting Register 0 (DIVR0) and Basic Clock Division Setting Register 1 (DIVR1).

  • Page 129: Block Diagram Of Clock Generation Controller

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.5 Block Diagram of Clock Generation Controller This section provides a block diagram of the clock generation controller. ■ Block Diagram Figure 3.12-1 shows a block diagram of the clock generation controller. Refer to "3.12.6 Register of Clock Generation Controller"...

  • Page 130: Register Of Clock Generation Controller

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.6 Register of Clock Generation Controller This section describes the functions of registers to be used in the clock generation controller. ■ Reset Source Register/Watchdog Timer Control Register (RSRR) Figure 3.12-2 shows the configuration of the reset source register/watchdog timer control register (RSRR).

  • Page 131

    CHAPTER 3 CPU AND CONTROL UNITS [bit13] WDOG (WatchDOG reset occurred) This bit indicates whether a reset (INIT) occurred due to the watchdog timer. Table 3.12-2 WDOG Function WDOG Function No reset (INIT) occurred due to the watchdog timer. A reset (INIT) occurred due to watchdog timer. •...

  • Page 132

    CHAPTER 3 CPU AND CONTROL UNITS ■ Standby Control Register (STCR) Figure 3.12-3 shows the configuration of the standby control register (STCR). Figure 3.12-3 Configuration of Standby Control Register (STCR) Bits Address: 00000481 STOP SLEEP SRST OSCD1 Initial value (INIT pin) Initial value (INIT) Initial value (RST) The standby control register (STCR) controls the operating mode of the device.

  • Page 133

    CHAPTER 3 CPU AND CONTROL UNITS [bit6] SLEEP (SLEEP mode) This bit specifies entry into stop mode. If "1" is written to both bit7 (STOP bit) and this bit, bit7 (STOP) has precedence and the device enters stop mode. Table 3.12-6 SLEEP Function SLEEP Function Sleep mode not entered (initial value)

  • Page 134

    CHAPTER 3 CPU AND CONTROL UNITS [bit3, bit2] OS1, OS0 (Oscillation Stabilization time select) These bits set the oscillation stabilization wait time used after a reset (INIT), return from stop mode, etc. The values written to these bits determine the interval of the watchdog timer, which can be selected from the four types shown in Table 3.12-9.

  • Page 135

    CHAPTER 3 CPU AND CONTROL UNITS ■ Time Base Counter Control Register (TBCR) Figure 3.12-4 shows the configuration of the time base counter control register (TBCR) bits. Figure 3.12-4 Configuration of Time Base Counter Control Register (TBCR) Bits Address: 00000482 TBIF TBIE TBC2...

  • Page 136

    CHAPTER 3 CPU AND CONTROL UNITS [bit13 to bit11] TBC2, TBC1, TBC0 (time-base timer Counting time select) These bits set the interval time of the time base counter that is used for the time-base timer. The values written to these bits determine the interval time, which can be selected from the eight types shown in Table 3.12-13.

  • Page 137

    CHAPTER 3 CPU AND CONTROL UNITS [bit8] SYNCS (SYNChronous Standby enable) This bit is the synchronous standby enable bit. Be sure to set "1" into this bit when using the standby mode (sleep or stop mode). Table 3.12-15 Function of synchronous standby operation enable bit (SYNCS) SYNCS Function Normal standby operation (initial value)

  • Page 138

    CHAPTER 3 CPU AND CONTROL UNITS ■ Clock Source Control Register (CLKR) Figure 3.12-6 shows the configuration of the clock source control register (CLKR) bits. Figure 3.12-6 Configuration of Clock Source Control Register (CLKR) Bits Address: 000484 Reserved Reserved CLKS1 CLKS0 PLL1S2 PLL1S1...

  • Page 139

    CHAPTER 3 CPU AND CONTROL UNITS [bit11] (Reserved) This bit is reserved. [bit10] PLL1EN (PLL1 ENable) This bit is the enable bit of the main PLL. Rewriting of this bit is disabled while the main PLL is selected as the clock source. Selection of the main PLL as the clock source is disabled while this bit is set to "0"...

  • Page 140

    CHAPTER 3 CPU AND CONTROL UNITS ■ Base Clock Division Setting Register 0 (DIVR0) Figure 3.12-7 shows the configuration of the Base Clock Division Setting Register 0 (DIVR0) bits. Figure 3.12-7 Configuration of Base Clock Division Setting Register 0 (DIVR0) Bits Address: 000486 Initial value (INIT) Initial value (RST)

  • Page 141

    CHAPTER 3 CPU AND CONTROL UNITS [bit15 to bit12] B3, B2, B1, B0 (clkB divide select 3 to 0) These bits are the clock divide-by rate setting bits of the CPU clock (CLKB). Set the clock divide-by rate of the CPU, internal memory, and internal bus clock (CLKB). The values written to these bits determine the divide-by rate (clock frequency) of the CPU and internal bus clock in relation to the base clock, which can be selected from the 16 types shown in Table 3.12-20.

  • Page 142

    CHAPTER 3 CPU AND CONTROL UNITS [bit11 to bit8] P3, P2, P1, P0 (clkP divide select 3 to 0) These bits are the clock divide-by rate setting bits of the peripheral clock (CLKP). Set the clock divide-by rate of the peripheral circuit and the peripheral bus clock (CLKP). The values written to these bits determine the divide-by rate (clock frequency) of the peripheral circuit and the peripheral bus clock in relation to the base clock, which can be selected from the 16 types shown in Table 3.12-21.

  • Page 143

    CHAPTER 3 CPU AND CONTROL UNITS ■ Base Clock Division Setting Register 1 (DIVR1) Figure 3.12-8 shows the configuration of the Base Clock Division Setting Register 1 (DIVR1) bits. Figure 3.12-8 Configuration of Base Clock Division Setting Register 1 (DIVR1) Bits Address: 00000487 Initial value (INIT) Initial value (RST)

  • Page 144

    CHAPTER 3 CPU AND CONTROL UNITS Note: The upper-limit frequency for operation is 68 MHz. Do not set a divide-by rate that results in a frequency exceeding this limit.

  • Page 145: Peripheral Circuits Of Clock Controller

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.7 Peripheral Circuits of Clock Controller This section describes the peripheral circuit functions of the clock controller. ■ Time Base Counter The clock controller has a 26-bit time base counter that runs on the system base clock. The time base counter is used to measure the oscillation stabilization wait time in addition to having the uses listed below (For more information about the oscillation stabilization wait time, see Section "3.11.4 Oscillation Stabilization Wait Time").

  • Page 146

    CHAPTER 3 CPU AND CONTROL UNITS [Suspending the watchdog timer (automatic postponement)] If program operation stops on the CPU, the watchdog reset generation flag is initialized and generation of a watchdog reset is postponed. Stopping of program operation specifically refers to the following statuses: •...

  • Page 147

    CHAPTER 3 CPU AND CONTROL UNITS [Clearing of the time base counter due to the device state] All bits of the time base counter are cleared to "0" at the same time if the device enters one of the following states: •...

  • Page 148: Smooth Startup And Stop Of Clock

    CHAPTER 3 CPU AND CONTROL UNITS 3.12.8 Smooth Startup and Stop of Clock This section explains the method to control the internal voltage effect and voltage surge. ■ Smooth Startup and Stop of Clock Connect the bypass capacitor of about 5.0µF to the C pin to control the internal voltage effect or voltage surge so that the change of the internal voltage is controlled drastically.

  • Page 149

    CHAPTER 3 CPU AND CONTROL UNITS ■ Program Example of Smooth Startup and Stop of Clock ❍ Procedure of startup #macro wait_loop loop_number #local _wait64_loop ldi #loop_number,r0 _wait64_loop: #-1,r0 _wait64_loop #endm smooth_up_start3: #_DIVR0,r1 // Division register for CLKB and CLKP #_DIVR1,r2 // Division register for CLKT #_CLKR,r3...

  • Page 150

    CHAPTER 3 CPU AND CONTROL UNITS ❍ Procedure of shut down #macro wait_loop loop_number #local _wait64_loop #loop_number,r0 _wait64_loop: #-1,r0 bne _wait64_loop #endm smooth_down_start3: #_DIVR0,r1 // Division register for CLKB and CLKP #_DIVR1,r2 // Division register for CLKT #_CLKR,r3 // CLKR register #0x11,r5 #0x3f,r6 #0xff,r8...

  • Page 151: Device State Control

    CHAPTER 3 CPU AND CONTROL UNITS 3.13 Device State Control This section describes the states of the FR family and their control. It also describes low-power mode. ■ Device States The FR family has the operating states listed below. For more information about these states, see Section "3.13.1 Device States and State Transitions".

  • Page 152

    CHAPTER 3 CPU AND CONTROL UNITS ■ State of Device and Each Transition The following shows the device state transitions of the MB91301 series. 1 INIT pin = 0(INT) Priority order of transition 2 INIT pin = 1(INIT release) 3 Oscillation stabilization wait end Power-on 4 RESET (RST) release High...

  • Page 153: Device States And State Transitions

    CHAPTER 3 CPU AND CONTROL UNITS 3.13.1 Device States and State Transitions This section describes device operating states and the transition between operating states. ■ RUN State (Normal Operation) In the RUN state, a program is being executed. All internal clocks are supplied and all circuits are enabled.

  • Page 154

    CHAPTER 3 CPU AND CONTROL UNITS ■ Oscillation Stabilization Wait RUN State In the oscillation stabilization wait RUN state, the device is stopped. This state occurs after a return from the stop state. All internal circuits except the clock generation controller (time base counter and device state controller) are stopped.

  • Page 155

    CHAPTER 3 CPU AND CONTROL UNITS ■ Settings Initialization Reset (INIT) State In the settings initialization reset (INIT) state, all settings are initialized. This state occurs if a settings initialization reset (INIT) is accepted. Execution of a program on the CPU is stopped and the program counter is initialized. All peripheral circuits are initialized.

  • Page 156: Low-power Modes

    CHAPTER 3 CPU AND CONTROL UNITS 3.13.2 Low-power Modes This section describes the low-power modes, some MB91301 series states, and how to use the low-power modes. ■ Low-power Modes The FR family has the following low-power modes: • Sleep mode:The device enters the sleep state due to writing to a register. •...

  • Page 157

    CHAPTER 3 CPU AND CONTROL UNITS ❍ Circuits that stop in the sleep state • Program execution on the CPU • Bit search module (enabled if DMA transfer occurs) • Various built-in memory (enabled if DMA transfer occurs) • Internal types of and external buses (enabled if DMA transfer occurs. A bus request is enabled.) ❍...

  • Page 158

    CHAPTER 3 CPU AND CONTROL UNITS ■ Stop Mode If "1" is set for bit7 (STOP bit) of the standby control register (STCR), stop mode is initiated and the device enters the stop state. The stop state is maintained until a source for return from the stop state occurs.

  • Page 159

    CHAPTER 3 CPU AND CONTROL UNITS ❍ High impedance control of a pin in the stop state • If "1" is set for bit5 (HIZ bit) of the standby control register (STCR), the output of a pin in the stop state is set to the high impedance state. For information about pins subject to this control, see the appendix, "STATUS OF PINS IN THE CPU STATES".

  • Page 160: Operating Modes

    CHAPTER 3 CPU AND CONTROL UNITS 3.14 Operating Modes Two operating modes are provided: bus mode and access mode. This section describes these modes. ■ Operating Modes B u s m o d e A c c e s s m o d e 32-bit bus width External-ROM 16-bit bus width...

  • Page 161

    CHAPTER 3 CPU AND CONTROL UNITS ■ Mode Settings For the FR family, set the operating mode using the mode pins (MD2, MD1, and MD0) and the mode register (MODR). ❍ Mode pins Use the three mode pins (MD2, MD1, and MD0) to specify mode vector fetch and to set a test mode.

  • Page 162

    CHAPTER 3 CPU AND CONTROL UNITS [bit26] ROMA (Internal ROM enable bit) This bit sets whether to making built-in F-bus RAM and F-bus ROM region effective. Table 3.14-2 Function of internal ROM enable ROMA Function Remark Built-in F-bus region (40000 to 100000 ) becomes External ROM mode...

  • Page 163: Chapter 4 External Bus Interface

    CHAPTER 4 EXTERNAL BUS INTERFACE The external bus interface controller controls the interfaces with the internal bus for chips and with external memory and I/O devices. This chapter explains each function of the external bus interface and its operation. 4.1 Overview of the External Bus Interface 4.2 External Bus Interface Registers 4.3 Setting Example of the Chip Select Area 4.4 Endian and Bus Access...

  • Page 164: Overview Of The External Bus Interface

    CHAPTER 4 EXTERNAL BUS INTERFACE Overview of the External Bus Interface This section explains the features, block diagram, I/O pins, and registers of the external bus interface. ■ Features The external bus interface has the following features: ❍ Addresses of up to 32 bits (4 Gbytes space) can be output. ❍...

  • Page 165

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ A different detailed timing can be set for each access timing type. • For the same type of access timing, a different setting can be made in each chip select area. • Auto-wait can be set to up to 15 cycles (asynchronous SRAM, ROM, Flash, and I/O area). •...

  • Page 166

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Block Diagram Figure 4.1-1 Block Diagram of the External Bus Interface Internal address bus Internal data bus External data bus write buffer switch read buffer switch DATA BLOCK ADDRESS BLOCK +1 or +2 External address bus address buffer CS0 to CS7 comparator...

  • Page 167

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ I/O Pins The I/O pins are external bus interface pins (Some pins have other uses). The following lists the I/O pins for each interface: ❍ Ordinary bus interface • A31 to A00, D31 to D00 (AD15 to AD00) •...

  • Page 168

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Register List Figure 4.1-2 shows the registers used by the external bus interface: Figure 4.1-2 List of External Bus Interface Registers 24 23 16 15 ASR0 ACR0 ASR1 ACR1 ASR2 ACR2 ASR3 ACR3 Area Select Registers 0 to 7 (ASR0 to ASR7) ASR4 ACR4 Area Configuration Registers 0 to 7 (ACR0 to ACR7)

  • Page 169: External Bus Interface Registers

    CHAPTER 4 EXTERNAL BUS INTERFACE External Bus Interface Registers This section explains the registers used in the external bus interface. ■ Register Types The following registers are used by the external bus interface: • Area select registers (ASR0 to ASR7) •...

  • Page 170: Area Select Registers 0 To 7(asr0 To Asr7)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.1 Area Select Registers 0 to 7(ASR0 to ASR7) This section explains the configuration and functions of area select registers 0 to 7 (ASR0 to ASR7). ■ Configuration of Area Select Registers 0 to 7 (ASR0 to ASR7) The area select registers (ASR0 to ASR7: Area Select Registers 0 to 7) specify the start address of each chip select area of CS0 to CS7.

  • Page 171

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Functions of Bits in the Area Select Registers (ASR0 to ASR7) The area select registers (ASR0 to ASR7) specify the start address of each chip select area (CS0 to CS7). The start address can be set in the high-order 16 bits (bits A31 to A16). Each chip select area starts with the address set in this register and covers the range set by the four bits ASZ3 to ASZ0 of the ACR0 to ACR7 registers.

  • Page 172: Area Configuration Registers 0 To 7 (acr0 To Acr7)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.2 Area Configuration Registers 0 to 7 (ACR0 to ACR7) This section explains the configuration and functions of area configuration registers 0 to 7 (ACR0 to ACR7). ■ Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) The area configuration registers 0 to 7 (ACR0 to ACR7: FArea Configuration Register 0 to 7) set the function of each chip select area.

  • Page 173

    CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value ACR6H INIT Access Address 00065A ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 XXXXXXXX XXXXXXXX ACR6L Address 00065B SREN PFEN WREN LEND TYP3 TYP2 TYP1 TYP0 XXXXXXXX XXXXXXXX ACR7H Address 00065E ASZ3 ASZ2 ASZ1 ASZ0 DBW1 DBW0 BST1 BST0 XXXXXXXX XXXXXXXX ACR7L Address 00065F...

  • Page 174

    CHAPTER 4 EXTERNAL BUS INTERFACE ASZ3 to ASZ0 are used to set the size of each area by modifying the number of comparison of bits to ASR. Thus, an ASR contains bits that are not compared. Bits ASZ3 to ASZ0 of ACR0 are initialized to 1111 ) by RST.

  • Page 175

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit7] SREN (ShaRed Enable) This bit sets enabling or disabling of sharing of each chip select area by BRQ/BGRNT as indicated in the following table. Table 4.2-4 Enabling or disabling of sharing of each chip select area by BRQ/BGRNT SREN Sharing enable/disable Disable sharing by BRQ/BGRNT(CSn cannot be high impedance)

  • Page 176

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit4] LEND (Little ENDian select) This bit sets the order of bytes of each chip select area as indicated in the following table. Table 4.2-7 Setting of byte ordering to each chip select area LEND Order of bytes Big endian Little endian...

  • Page 177

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ CS area mask setting function If you want to set an area some of whose operation settings are changed for a certain CS area (referred to as the base setting area), you can set TYPE3 to TYPE0 of ARC in another CS area to "1111 "...

  • Page 178: Area Wait Register (awr0 To Awr7)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.3 Area Wait Register (AWR0 to AWR7) This section explains the configuration and functions of the area wait registers (AWR0 to AWR7). ■ Configuration of the Area Wait Registers (AWR0 to AWR7) The area wait registers (AWR0 to AWR7: Area Wait Register 0 to 7) specify various kinds of waits for each chip select area.

  • Page 179

    CHAPTER 4 EXTERNAL BUS INTERFACE (Continued) Initial value AWR6H INIT Access Address 00066C XXXXXXXX XXXXXXXX AWR6L Address 00066D XXXXXXXX XXXXXXXX AWR7H Address 00066E XXXXXXXX XXXXXXXX AWR7L Address 00066F XXXXXXXX XXXXXXXX The function of each bit changes according to the access type (TYP3 to TYP0 bits) setting of the ACR0 to ACR7 registers.

  • Page 180

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit15 to bit12] W15 to W12 (First Access Wait Cycle) These bits set the number of auto-wait cycles to be inserted into the first access cycle of each cycle. Except for the burst access cycles, only this wait setting is used. The initial value of the CS0 area is set to 7 waits.

  • Page 181

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit7, bit6] W07, W06 (Read -> Write Idle Cycle) The read -> write idle cycle is set to prevent collision of read data and write data on the data bus when a write cycle follows a read cycle. During an idle cycle, all chip select signals are negated and the data terminals maintain the high impedance state.

  • Page 182

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit3] W03 (WR0 to WR3, WRn Output Timing Selection) The WR0 to WR3, WRn output timing setting selects whether to use write strobe output as an asynchronous strobe or synchronous write enable. The asynchronous strobe setting corresponds to normal memory/ I/O.

  • Page 183

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit2] W02 (Address -> CSn Delay) The address -> CSn delay setting is made when a certain type of setup is required for the address when CSn falls or CSn edges are needed for successive accesses to the same chip select area.

  • Page 184

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit0] W00 (RD/WRn -> CSn Hold Extension Cycle) The RD/WRn -> CSn hold extension cycle is set to extend the period before negating CSn after the read/write strobe is negated. One hold extension cycle is inserted before CSn is negated after the read/write strobe is negated.

  • Page 185

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit11] W11: Reserved bit Be sure to set this bit to "0". [bit10 to bit8] W10 to W08 (CAS latency Cycle): CAS latency Set these bits to the CAS latency. Table 4.2-20 lists the settings for the CAS latency. Table 4.2-20 CAS Latency Setting CAS latency 1 cycle...

  • Page 186

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit3, bit2] W03, W02 (RAS Active time): RAS active time Set these bits to the minimum number of cycles for RAS active time. Table 4.2-23 lists the settings for RAS active time. Table 4.2-23 RAS Active Time RAS active time 1 cycle 2 cycles...

  • Page 187: Memory Setting Register (mcra For Sdram/fcram Auto-precharge Off Mode)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.4 Memory Setting Register (MCRA for SDRAM/FCRAM auto-precharge OFF mode) This section describes the configuration and the function of memory setting register (MCRA for SDRAM/FCRAM auto-precharge OFF mode). ■ Structure of the Memory Setting Register (MCRA for SDRAM/FCRAM Auto-precharge OFF Mode) Memory setting register (MCRA for SDRAM/FCRAM auto-precharge OFF mode) The memory setting register (MCRA: Memory Setting Register for extend type-A for SDRAM/ FCRAM auto-precharge OFF mode) is used to make various settings for SDRAM/FCRAM...

  • Page 188

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit27] WBST (Write BurST enable): Write burst setting Set this bit to select whether to burst-write for write access. Table 4.2-27 lists the settings for burst write. Table 4.2-27 Settings for Burst Write WBST Settings for burst write Single write Burst write For connecting FCRAM, be sure to set the bit to "1".

  • Page 189: Memory Setting Register (mcrb For Fcram Auto-precharge On Mode)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.5 Memory Setting Register (MCRB for FCRAM auto-precharge ON mode) This section describes the memory setting register (MCRB for FCRAM auto-precharge ON mode). ■ Structure of the Memory Setting Register (MCRB for FCRAM Auto-precharge ON Mode) Settings for Memory configuration register (MCRB: Memory Configuration Register for extend type-B for FCRAM auto-precharge ON mode) is used to make various settings for FCRAM connected to the chip select area.

  • Page 190: I/o Wait Registers For Dmac (iowr0, Iowr1)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.6 I/O Wait Registers for DMAC (IOWR0, IOWR1) This section explains the configuration and functions of the I/O wait registers for DMAC (IOWR0, IOWR1). ■ Configuration of the I/O Wait Registers for DMAC (IOWR0, IOWR1) The I/O wait registers for DMAC (IOWR0, IOWR1: I/O Wait Register for DMAC0, DMAC1) set various kinds of waits during DMA fly-by access.

  • Page 191

    CHAPTER 4 EXTERNAL BUS INTERFACE If "0" is set, the read strobe signal (RD for memory -> I/O and IORD for I/O -> memory) and the write strobe signal (IOWR for memory -> I/O and WR0 to WR3 and WR for I/O -> memory) on the transfer source access side are output at the same timing.

  • Page 192: Chip Select Enable Register (cser)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.7 Chip Select Enable Register (CSER) The chip select enable register (CSER) set up the access permit of each chip select area. ■ Configuration of the Chip Select Enable Register (CSER) The chip select enable register (CSER: Chip Select Enable register) enables and disables each chip select area.

  • Page 193

    CHAPTER 4 EXTERNAL BUS INTERFACE Table 4.2-36 lists the corresponding CSn for the chip select enable bits. Table 4.2-36 CSn Corresponding to the Chip Select Enable Bits CSE bit Corresponding CSn bit24: CSE0 bit25: CSE1 bit26: CSE2 bit27: CSE3 bit28: CSE4 bit29: CSE5 bit30: CSE6 bit31: CSE7...

  • Page 194: Cache Enable Register (cher)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.8 Cache Enable Register (CHER) This section explains the configuration and functions of the cache enable register (CHER). ■ Configuration of the Cache Enable Register (CHER) The cache enable register (CHER: CacHe Enable Register) controls the transfer of data read from each chip select area.

  • Page 195: Pin/timing Control Register (tcr)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.9 Pin/Timing Control Register (TCR) This section explains the configuration and functions of the pin/timing control register and its function. ■ Configuration of the Pin/Timing Control Register (TCR) The pin/timing control register (TCR: Terminal and Timiting Control Register) controls the functions related to the general external bus interface controller, such as the setting of common pin functions and timing control.

  • Page 196

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit5] PCLR (Prefetch buffer clear) This bit completely clears the prefetch buffer. Table 4.2-40 Function of prefetch buffer control PCLR Prefetch buffer control Normal state Clear the prefetch buffer. If "1" is written, the prefetch buffer is cleared completely. When clearing is completed, the bit value automatically returns to "0".

  • Page 197: Refresh Control Register (rcr)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.2.10 Refresh Control Register (RCR) This section describes the bit configuration and functions of the refresh control register (RCR). ■ Structure of the Refresh Control Register (RCR) The refresh control register (RCR) is used to make various refresh control settings for SDRAM. The setting of this register is meaningless as long as SDRAM control is not set for any area, in that case the register value must not be updated from the initial state.

  • Page 198

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Bit Functions of the Refresh Control Register (RCR) The following summarizes the functions of individual bits in the refresh control register (RCR). [bit31] SELF (SELF refresh assert): Self-refresh control This bit is used to control the self-refresh mode for memory that supports the self-refresh mode.

  • Page 199

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit29 to bit24] RFINT5 to RFINT0 (ReFresh INTerval): Auto-refresh interval Set these bits to the interval for automatic refreshing. The auto-refresh interval can be obtained for distributed refresh mode {(REFINT5 to REFINT0 value) x 32 x (external bus clock cycle)} or for centralized refresh mode {(REFINT5 to REFINT0 value) x 32 x (RFC specified number of times) x (external bus clock cycle)} Calculate the design value in consideration of the maximum RAS active time.

  • Page 200

    CHAPTER 4 EXTERNAL BUS INTERFACE [bit19] PON (Power ON): Power-on control This bit is used to control the SDRAM (FCRAM) power-on sequence. Table 4.2-46 shows the function of power-on control. Table 4.2-46 Function of Power-on Control Power-on control Disabled (no-operation) Start power-on sequence Writing "1"...

  • Page 201: Setting Example Of The Chip Select Area

    CHAPTER 4 EXTERNAL BUS INTERFACE Setting Example of the Chip Select Area In the external bus interface, a total of eight chip select areas can be set. This section presents an example of setting the chip select area. ■ Example of Setting the Chip Select Area The address space of each area can be placed, in units of a minimum of 64K bytes, anywhere in the 4 Gbytes space using ASR0 to ASR7 (Area Select Registers) and ACR0 to ACR7 (Area Configuration Registers).

  • Page 202: Endian And Bus Access

    CHAPTER 4 EXTERNAL BUS INTERFACE Endian and Bus Access There is a one-to-one correspondence between the WR0 to WR3 control signal and the byte location regardless of the data bus width. The following summarizes the location of bytes on the data bus of the FR family used according to the specified data bus width and the corresponding control signal for each bus mode.

  • Page 203

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ SDRAM (FCRAM) Interface Figure 4.4-3 Data Bus Width of the SDRAM (FCRAM) Interface and Its Control Signals a)32-bit bus width b)16-bit bus width c)8-bit bus width Data bus Control signal Data bus Control signal Data bus Control signal DQMUU DQMUU DQMUU...

  • Page 204: Big Endian Bus Access

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.1 Big Endian Bus Access With the exception of the CS0 area of the FR family, either the big endian method or the little endian method can be selected for each chip select area. If "0" is set for the LEND bit of the ACR register, the area is treated as big endian.

  • Page 205

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Byte access (LDUB/STB instruction executed) Figure 4.4-6 Relationship between Internal Register and External Data Bus for Byte Access a) Output address b) Output address c) Output address d) Output address low-order digits "00 " low-order digits "01 "...

  • Page 206

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ 8-bit bus width Figure 4.4-9 Relationship between Internal Register and External Bus Having 8-bit Bus Width Internal register External bus Output address low-order digits "00 " "01 " "10 " "11 " read/write...

  • Page 207

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ External Bus Access Figure 4.4-10, Figure 4.4-11 and Figure 4.4-12 show external bus access (32-bit/16-bit/8-bit bus width) separately for word, halfword, and byte access. The following items are included in Figure 4.4-10, Figure 4.4-11 and Figure 4.4-12: •...

  • Page 208

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ 16-bit bus width Figure 4.4-11 External Bus Access for 16-bit Bus Width (A) Word access (a) PA1/PA0=00 (b) PA1/PA0=01 (c) PA1/PA0=10 (d) PA1/PA0=11 (1) Output A1/A0=00 (1) Output A1/A0=00 (1) Output A1/A0=00 (1) Output A1/A0=00 (2) Output A1/A0=10 (2) Output A1/A0=10 (2) Output A1/A0=10...

  • Page 209

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ 8-bit bus width Figure 4.4-12 External Bus Access for 8-bit Bus Width (A) Word access (a) PA1/PA0=00 (b) PA1/PA0=01 (c) PA1/PA0=10 (d) PA1/PA0=11 (1) Output A1/A0=00 (1) Output A1/A0=00 (1) Output A1/A0=00 (1) Output A1/A0=00 (2) Output A1/A0=01 (2) Output A1/A0=01 (2) Output A1/A0=01...

  • Page 210

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Example of Connection with External Devices Figure 4.4-13 shows an example of connecting the FR family to external devices. Figure 4.4-13 Example of Connecting the FR Family to External Devices MB91301 series * For 16-/8-bit devices, use the data bus on the MSB side of MB91301 series D24 D23 D16 D15...

  • Page 211: Little Endian Bus Access

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.2 Little Endian Bus Access On the FR family, each chip can switch between the big endian and little endian methods independently from others, except the CS0 area. When the LEND bit in the area configuration register (ACR) is set to "1", the corresponding area is handled in the little endian method.

  • Page 212

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Data Format The relationship between the internal register and external data bus is as follows: ❍ Word access (when executing the LD/ST instructions) Figure 4.4-14 Relationship between the Internal Register and External Data Bus for Word Access Internal register External bus ❍...

  • Page 213

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Data Bus Width The following shows the relationships between the internal register and external data bus for each data bus width. ❍ 32-bit bus width Figure 4.4-17 Relationship between Internal Register and External Bus Data for 32-bit Bus Width Internal register External bus Read/Write...

  • Page 214

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Examples of Connection with External Devices The following shows examples of connecting the FR family to external devices for each bus width. ❍ 32-bit bus width Figure 4.4-20 Example of Connecting the FR Family to External Devices (32-bit Bus Width) MB91301 series D24 D23 D16 D15...

  • Page 215

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ 8-bit bus width Figure 4.4-22 Example of Connecting the FR Family to External Devices (8-bit Bus Width) MB91301 series big endian area little endian area...

  • Page 216: Comparison Of Big Endian And Little Endian External Access

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.4.3 Comparison of Big Endian and Little Endian External Access This section shows a comparison of big endian and little endian external access in word access, halfword access, and byte access for each bus width. When data bus is connected according to examples of connecting to external devices as shown in Sections "4.4.1 Big Endian Bus Access"...

  • Page 217

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Halfword Access Big endian mode Little endian mode Internal External Control Internal External Control register terminal terminal register terminal terminal address : "0" address : "0" 32-bit bus width Internal External Control Internal External Control register terminal...

  • Page 218

    CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode Little endian mode Internal External Control Internal External Control register terminal terminal register terminal terminal address: "0" address: "0" 16-bit bus width Internal External Control Internal External Control register terminal terminal register terminal terminal address: "2"...

  • Page 219

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Byte Access Big endian mode Little endian mode Internal External Control Internal External Control register terminal terminal register terminal terminal address : "0" address : "0" Internal External Control Internal External Control register terminal terminal register terminal...

  • Page 220

    CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode Little endian mode Internal External Control Internal External Control register terminal terminal register terminal terminal address: "0" address: "0" Internal External Control Internal External Control register terminal terminal register terminal terminal address: "1" address: "1"...

  • Page 221

    CHAPTER 4 EXTERNAL BUS INTERFACE Big endian mode Little endian mode Internal External Control Internal External Control register terminal terminal register terminal terminal address: "0" address: "0" Internal External Control Internal External Control register terminal terminal register terminal terminal address: "1" address: "1"...

  • Page 222: Operation Of The Ordinary Bus Interface

    CHAPTER 4 EXTERNAL BUS INTERFACE Operation of the Ordinary Bus Interface This section explains operation of the ordinary bus interface. ■ Ordinary Bus Interface For the ordinary bus interface, two clock cycles are the basic bus cycles for both read access and write access.

  • Page 223: Basic Timing

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.1 Basic Timing This section shows the basic timing for successive accesses. ■ Basic Timing (For Successive Accesses) Figure 4.5-1 shows the operation timing for (TYP3 to TYP0 = 0000 , AWR = 0008 Figure 4.5-1 Basic Timing (For Successive Accesses) MCLK A31 to A00 READ...

  • Page 224: Operation Of Wrn + Byte Control Type

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.2 Operation of WRn + Byte Control Type This section shows the operation timing for the WRn + byte control type. ■ Operation Timing of the WRn + Byte Control Type Figure 4.5-2 shows the operation timing for (TYP3 to TYP0 = 0010 , AWR = 0008 Figure 4.5-2 Timing Chart for the WRn + Byte Control Type MCLK...

  • Page 225

    CHAPTER 4 EXTERNAL BUS INTERFACE • WR0 to WR3 indicate the byte location expressed with negative logic when they are used for access as the byte enable signal. Assertion continues from the bus access start cycle to the bus access end cycle and changes at the same timing as the address timing. The byte location for access is indicated for both read access and write access.

  • Page 226: Read -> Write Operation

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.3 Read -> Write Operation This section shows the operating timing for read -> write. ■ Operation Timing of Read -> Write Figure 4.5-3 shows the operation timing for (TYP3 to TYP0=0000 , AWR=0048 Figure 4.5-3 Timing Chart for Read -> Write Read Idle Write...

  • Page 227: Write -> Write Operation

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.4 Write -> Write Operation This section shows the operation timing for write -> write. ■ Write -> Write Operation Figure 4.5-4 shows the operation timing for (TYP3 to TYP0=0000 , AWR=0018 Figure 4.5-4 Timing Chart for the Write -> Write Operation Read Write recovery Write...

  • Page 228: Auto-wait Cycle

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.5 Auto-Wait Cycle This section shows the operation timing for the auto-wait cycle. ■ Auto-Wait Cycle Timing Figure 4.5-5 shows the operation timing for (TYP3 to TYP0=0000 , AWR=2008 Figure 4.5-5 Timing Chart for the Auto-Wait Cycle Basic cycle Wait cycle MCLK...

  • Page 229: External Wait Cycle

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.6 External Wait Cycle This section shows the operation timing for the external wait cycle. ■ External Wait Cycle Timing Figure 4.5-6 shows the operation timing for (TYP3 to TYP0=0001 , AWR=2008 Figure 4.5-6 Timing Chart for the External Wait Cycle Basic cycle 2 auto-wait cycles Wait cycle by RDY MCLK...

  • Page 230: Synchronous Write Enable Output

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.7 Synchronous Write Enable Output This section shows the operation timing for synchronous write enable output. ■ Operation Timing for Synchronous Write Enable Output Figure 4.5-7 shows the operation timing for (TYP3 to TYP0=0000 , AWR=0000 Figure 4.5-7 Timing Chart for Synchronous Write Enable Output MCLK A31 to A00...

  • Page 231

    CHAPTER 4 EXTERNAL BUS INTERFACE • If synchronous write enable output is used, the following restrictions apply: Do not set the following additional wait because the timing for synchronous write enable output becomes meaningless: - CS -> RD/WRn setup (Always write "0" to the W01 bit of AWR) - First wait cycle setting (Always write "0000 "...

  • Page 232: Csn Delay Setting

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.8 CSn Delay Setting This section shows the operation timing for the CSn delay setting. ■ Operation Timing for the CSn Delay Setting Figure 4.5-8 shows the operation timing for (TYP3 to TYP0=0000 , AWR=000C Figure 4.5-8 Operation Timing Chart for the CSn Delay Setting MCLK A31 to A00...

  • Page 233: Csn -> Rd/wrn Setup And Rd/wrn -> Csn Hold Setting

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.9 CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Setting This section shows the operation timing for the CSn -> RD/WRn setup and RD/WRn -> CSn hold settings. ■ Operation Timing for the CSn -> RD/WRn Setup and RD/WRn -> CSn Hold Settings Figure 4.5-9 shows the operation timing for (TYP3 to TYP0=0000 AWR=000B Figure 4.5-9 Timing Chart for the CSn ->...

  • Page 234: Dma Fly-by Transfer (i/o -> Memory)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.10 DMA Fly-By Transfer (I/O -> Memory) This section shows the operation timing for DMA fly-by transfer (I/O -> memory). ■ Operation Timing for DMA Fly-By Transfer (I/O -> Memory) Figure 4.5-10 shows the operation timing for (TYP3 to TYP0=0000 , AWR=0008 , IOWR=51 This timing chart shows a case in which a wait is not set on the memory side.

  • Page 235: Dma Fly-by Transfer (memory -> I/o)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.5.11 DMA Fly-By Transfer (Memory -> I/O) This section shows the operation timing for DMA fly-by transfer (memory -> I/O). ■ Operation Timing for DMA Fly-By Transfer (Memory -> I/O) Figure 4.5-11 shows the operation timing chart for (TYP3 to TYP0=0000 , AWR=0008 IOWR=51 ).

  • Page 236: Burst Access Operation

    CHAPTER 4 EXTERNAL BUS INTERFACE Burst Access Operation In the external bus interface, the operation that transfers successive data items in one access sequence is called burst access. The normal access cycle (that is, not burst access) is called single access. One access sequence starts with an assertion of AS and CSn and ends with negation of CSn.

  • Page 237

    CHAPTER 4 EXTERNAL BUS INTERFACE • The access sequence when burst cycles are used can be divided into the following two types: - First access cycle The first access cycle is the start cycle for the burst access and operates in the same way as the normal single access cycle.

  • Page 238: Address/data Multiplex Interface

    CHAPTER 4 EXTERNAL BUS INTERFACE Address/data Multiplex Interface This section explains the following three cases of operation of the address/data multiplex interface: • Without external wait • With external wait • CSn -> RD/WRn setup ■ Without External Wait Figure 4.7-1 shows the operation timing chart for (TYP3 to TYP0=0100 , AWR=0008 Figure 4.7-1 Timing Chart for the Address/Data Multiplex Interface (without External Wait) MCLK...

  • Page 239

    CHAPTER 4 EXTERNAL BUS INTERFACE • As with a normal interface, the address indicating the start of access is output to A31 to A0 during the time division bus cycle. Use this address if you want to use an address more than 8/16 bits in the address/data multiplex interface.

  • Page 240

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ CSn -> RD/WRn Setup Figure 4.7-3 shows the operation timing chart for (TYP3 to TYP0=0101 , AWR=100B Figure 4.7-3 Timing Chart for the Address/Data Multiplex Interface (CSn -> RD/WRn Setup) MCLK address[31:0] A31 to A00 READ D31 to D16 data[15:0]...

  • Page 241: Prefetch Operation

    CHAPTER 4 EXTERNAL BUS INTERFACE Prefetch Operation This section explains the prefetch operation. ■ Prefetch Operation The external bus interface controller contains a prefetch buffer consisting of 16 x 8 bits. If the PSUS bit of the TCR register is "0" and read access to an area to which the PFEN bit of the ACR register is set to "1"...

  • Page 242

    CHAPTER 4 EXTERNAL BUS INTERFACE starts at the new bank address. In SDRAM/FCRAM-connected areas, prefetch is also temporarily stopped, even if the page address is undated when write access to a prefetched area causes a page error or when access is made to another SDRAM/FCRAM area in which prefetch is not enabled.

  • Page 243

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Reading from the prefetch buffer Data stored in the prefetch buffer is read in response to access from the internal bus if an address matches, and no external access is performed. In reading from the buffer, addresses can be hit (up to 16 bytes) if they are in the forward direction but not continuous, so that a second read from the external bus is avoided, if possible, even for a short forward branch.

  • Page 244: Sdram/fcram Interface Operation

    CHAPTER 4 EXTERNAL BUS INTERFACE SDRAM/FCRAM Interface Operation This section describes the operations of the SDRAM/FCRAM interface. ■ SDRAM/FCRAM Interface The CS6 and CS7 areas can be used as SDRAM/FCRAM space by setting the TYP3 to TYP0 bits in the area configuration register (ACR) to "100X ".

  • Page 245

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Burst Read/Write Operation Timing Figure 4.9-1 shows the operation timings assuming that page hits and CAS latency "2" are set. Figure 4.9-1 Burst Read/Write Timing Chart MCLK SRAS,SCAS, READ WRITE Write Cas Latency recovery Write cycle Read cycle •...

  • Page 246

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Single Read Operation Timing Figure 4.9-3 shows the operation timings assuming that page misses, CAS latency "3", and no auto-precharge are set. Figure 4.9-3 Single Read Timing Chart MCLK SRAS,SCAS, READ RAS → CAS delay RAS precharge cycle Cas Latency (tRP)

  • Page 247

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Auto-refresh Operation Timing Figure 4.9-5 shows auto-refresh operation timings. Figure 4.9-5 Auto-refresh Timing Chart MCLK SRAS,SCAS, ACTV Refresh cycle • The refresh command is issued every "refresh control register's (RCR's) RFINT5 to RFINT0 value x 32" cycles and access is restarted upon completion of each refresh. •...

  • Page 248: Self Refresh

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.1 Self Refresh This section describes self-refreshing. ■ Self Refresh Writing "1" to the SELF bit in the refresh control register (RCR) causes the SDRAM/FCRAM interface to initiate the self-refresh transition sequence. After executing auto-refreshing the number of times set in the RFC2 to RFC0 bits, the SDRAM/ FCRAM interface issues the SELF command to SDRAM/FCRAM to enter the self-refresh mode.

  • Page 249: Power-on Sequence

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.2 Power-on Sequence This section describes the power-on sequence. ■ Power-on Sequence Setting the PON bit in the refresh control register (RCR) to "1" initiates the power-on sequence. Take the following steps to set the PON bit to "1" for transition to the power-on sequence. 1) Reserve the clock stabilization wait time specified in the SDRAM/FCRAM manual.

  • Page 250: Connecting Sdram/fcram To Many Areas

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.3 Connecting SDRAM/FCRAM to Many Areas This section shows the connecting SDRAM/FCRAM to many areas. ■ Connecting SDRAM/FCRAM to Many Areas SDRAM/FCRAM can be set for CS6 and CS7 areas. When connecting SDRAM/FCRAM to 2 areas, connect the same type of modules.

  • Page 251: Address Multiplexing Format

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.4 Address Multiplexing Format This section describes the address multiplexing format. ■ Address Multiplexing Format SDRAM/FCRAM access addresses correspond to row, bank, and column addresses differently depending on the settings of the ASZ3 to ASZ0, DBW1 and DBW0, PSZ2 to PSZ0, and BANK bits.

  • Page 252: Memory Connection Example

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.9.5 Memory Connection Example This section shows the memory connection example. ■ Memory Connection Example The SDRAM/FCRAM interface is connected to SDRAM/FCRAM as shown in Table 4.9-1 in principle. Table 4.9-1 SDRAM/FCRAM Interface to SDRAM/FCRAM Connection Table SDRAM/ FCRAM SDRAM/...

  • Page 253

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Using 8-bit SDRAM/FCRAM (Big endian) Total data bus width of 32 bits: Use four SDRAM/FCRAM modules. Total data bus width of 16 bits: Use two SDRAM/FCRAM modules. Figure 4.9-7 shows how to use 64-Mbit SDRAM (one bank address and 12 row addresses). Figure 4.9-7 Using 64-Mbit SDRAM This LSI DQMUU...

  • Page 254

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Using 16-bit SDRAM/FCRAM Total data width of 32 bits: Use two or four SDRAM modules. Total data width of 16 bits: Use one or two SDRAM modules. Figure 4.9-8 shows how to use 64-Mbit SDRAM (two bank addresses and 12 row addresses). Figure 4.9-8 Using 64-Mbit SDRAM This LSI DQMUU...

  • Page 255

    CHAPTER 4 EXTERNAL BUS INTERFACE ❍ Using 32-bit SDRAM When the data width is 32 bits: Use one or two SDRAM modules. Figure 4.9-9 shows 64-Mbit SDRAM (one bank address and 12 row addresses). Figure 4.9-9 Using 64-Mbit This LSI DQMUU DQMLU CS7 CS6...

  • Page 256: Dma Access Operation

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10 DMA Access Operation This section explains DMA access operation. ■ DMA Access Operation This section explains the following nine DMA operations: • DMA fly-by transfer (I/O -> memory) • DMA fly-by transfer (memory -> I/O) •...

  • Page 257: Dma Fly-by Transfer (i/o -> Memory)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.1 DMA Fly-By Transfer (I/O -> Memory) This section explains DMA fly-by transfer (I/O -> memory). ■ DMA Fly-By Transfer (I/O -> Memory) Figure 4.10-1 shows the operation timing chart for (TYP3 to TYP0=0000 , AWR=0008 IOWR=41 Figure 4.10-1 shows a case when a wait is not set on the memory side.

  • Page 258

    CHAPTER 4 EXTERNAL BUS INTERFACE • The CSn -> RD/WRn setup delay (W01 bit) and RD/WRn -> CSn hold delay (W00 bit) can be set independently. • When successive accesses are made within the same chip select area without negating the chip select, neither CSn ->...

  • Page 259: Dma Fly-by Transfer (memory -> I/o)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.2 DMA Fly-By Transfer (Memory -> I/O) This section explains DMA fly-by transfer (memory -> I/O). ■ DMA Fly-By Transfer (Memory -> I/O) Figure 4.10-2 shows the operation timing chart for (TYP3 to TYP0=0000 , AWR=0008 IOWR=41 Figure 4.10-2 shows a case in which a wait is not set on the memory side.

  • Page 260

    CHAPTER 4 EXTERNAL BUS INTERFACE • If wait is also set on the memory side (AWR15 to AWR12 is not "0"), the larger value is used as the wait cycle after comparison with the I/O wait (IW3 to IW0 bits). Reference: For memory on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated.

  • Page 261: Dma Fly-by Transfer (i/o -> Sdram/fcram)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.3 DMA Fly-By Transfer (I/O -> SDRAM/FCRAM) This section describes the operation of DMA fly-by transfer (I/O device to SDRAM/ FCRAM). ■ DMA Fly-By Transfer (I/O -> SDRAM/FCRAM) Figure 4.10-3 shows an operation timing chart assuming TYP3 to TYP0 set to 1000 , AWR set to 0051 , and IOWR set to 41...

  • Page 262

    CHAPTER 4 EXTERNAL BUS INTERFACE • For the I/O device on the data output side, a read strobe of three bus cycles extended by the I/O wait cycle and I/O hold wait cycle is generated. • For SDRAM/FCRAM on the receiving side, a WRIT command is issued at the timing that allows writing after the I/O wait cycle.

  • Page 263: Dma Fly-by Transfer (sdram/fcram -> I/o)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.4 DMA Fly-By Transfer (SDRAM/FCRAM -> I/O) This section describes the operation of DMA fly-by transfer (SDRAM/FCRAM device to I/O). ■ DMA Fly-By Transfer (SDRAM/FCRAM -> I/O) Figure 4.10-4 shows an operation timing chart assuming TYP3 to TYP0 set to 1000 , AWR set to 0051 , and IOWR set to 42...

  • Page 264

    CHAPTER 4 EXTERNAL BUS INTERFACE If SDRAM access is shorter than I/O access, the SDRAM access is extended by the I/O access (base access plus I/O wait). Figure 4.10-5 shows an operation timing chart assuming TYP3 to TYP0 set to 1000 , AWR set to 0051 , and IOWR set to 42...

  • Page 265

    CHAPTER 4 EXTERNAL BUS INTERFACE • For the I/O device on the receiving side, a write strobe of two bus cycles extended by the I/O wait cycle is generated. The I/O hold wait cycle does not affect the write strobe. However, the CS signal is retained until the fly-by bus access cycles end.

  • Page 266

    CHAPTER 4 EXTERNAL BUS INTERFACE Figure 4.10-7 Timing Chart for Fly-by Penalty Solution Using External Wait Cycles Based on the CAS Signal (CL = 2) I/O hold wait SDRAM basic access I/O basic cycle External RDY wait MCLK Bank Column A31 to A00 Address Address...

  • Page 267: 2-cycle Transfer (internal Ram -> External I/o, Ram)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.5 2-Cycle Transfer (Internal RAM -> External I/O, RAM) This section explains 2-cycle transfer (internal RAM -> external I/O, RAM) operation. The timing is the same as for external I/O, RAM -> internal RAM. ■ 2-Cycle Transfer (Internal RAM -> External I/O, RAM) Figure 4.10-8 shows the operation timing chart for (TYP3 to TYP0=0000 , AWR=0008 IOWR=00...

  • Page 268: 2-cycle Transfer (external -> I/o)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.6 2-Cycle Transfer (External -> I/O) This section explains 2-cycle transfer (external -> I/O) operation. ■ 2-Cycle Transfer (External -> I/O) Figure 4.10-9 shows the operation timing chart for (TYP3 to TYP0=0000 , AWR=0008 IOWR=00 Figure 4.10-9 shows a case in which a wait is not set for memory and I/O.

  • Page 269: 2-cycle Transfer (i/o -> External)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.7 2-Cycle Transfer (I/O -> External) This section explains 2-cycle transfer (I/O -> external) operation. ■ 2-Cycle Transfer (I/O -> External) Figure 4.10-10 shows the operation timing chart for (TYP3 to TYP0=0000 , AWR=0008 IOWR=00 Figure 4.10-10 shows a case in which a wait is not set for memory and I/O.

  • Page 270: 2-cycle Transfer (i/o -> Sdram/fcram)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.8 2-Cycle Transfer (I/O -> SDRAM/FCRAM) This section describes the operation of 2-cycle transfer (I/O device to SDRAM/FCRAM). ■ 2-Cycle Transfer (I/O -> SDRAM/FCRAM) Figure 4.10-11 shows an operation timing chart assuming TYP3 to TYP0 set to 1000 , AWR set to 0051 , and IOWR set to 00...

  • Page 271: 2-cycle Transfer (sdram/fcram -> I/o)

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.10.9 2-Cycle Transfer (SDRAM/FCRAM -> I/O) This section describes the operation of 2-cycle transfer (SDRAM/FCRAM to I/O device). ■ 2-Cycle Transfer (SDRAM/FCRAM -> I/O) Figure 4.10-12 shows a timing chart for 2-cycle transfer (SDRAM/FCRAM to I/O). Figure 4.10-12 Timing Chart for 2-cycle Transfer (SDRAM/FCRAM to I/O) MCLK memory...

  • Page 272: Bus Arbitration

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.11 Bus Arbitration This section shows timing charts for releasing the bus right and for acquiring the bus right. ■ Releasing the Bus Right Figure 4.11-1 shows the timing chart for releasing the bus right. Figure 4.11-1 Timing Chart for Releasing the Bus Right MCLK A23 to A00...

  • Page 273

    CHAPTER 4 EXTERNAL BUS INTERFACE ■ Acquiring the Bus Right Figure 4.11-2 shows the timing chart for acquiring the bus right. Figure 4.11-2 Timing Chart for Acquiring the Bus Right MCLK A23 to A00 Read D31 to D16 BGRNT 1 cycle •...

  • Page 274: Procedure For Setting A Register

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.12 Procedure for Setting a Register This section explains the procedure for setting a register. ■ Procedure for Setting a Register Using the following procedures to make external bus interface settings: 1. Before rewriting the contents of a register, be sure to set the CSER register so that the corresponding area is not used (0).

  • Page 275: Notes On Using The External Bus Interface

    CHAPTER 4 EXTERNAL BUS INTERFACE 4.13 Notes on Using the External Bus Interface This section explains some notes when using the external bus interface. ■ Notes for Use If settings are made so that the area (TYP3 to TYP0=0x0x ) where WR0 to WR3 are used as a write strobe and the area (TYP3 to TYP0=0x1x ) where WR is used as a write strobe are mixed, be sure to make the following setting in all areas that will be used:...

  • Page 276

    CHAPTER 4 EXTERNAL BUS INTERFACE...

  • Page 277: Chapter 5 I/o Port

    CHAPTER 5 I/O PORT This chapter describes the I/O ports and the configuration and functions of registers. 5.1 Overview of the I/O Port 5.2 I/O Port Registers...

  • Page 278: Overview Of The I/o Port

    CHAPTER 5 I/O PORT Overview of the I/O Port This section provides an overview of the I/O port. ■ Basic Block Diagram of the I/O Port The MB91301 series interface can be used as an I/O port if settings are made so that the external bus interface or peripherals corresponding to pins do not use the pins as input/output pins.

  • Page 279

    CHAPTER 5 I/O PORT ■ I/O Port Modes The I/O port has the following three modes: ❍ Port input mode (PFR=0 & DDR=0) • PDR read: Reads the level of the corresponding external pin. • PDR write: Writes a setting value to the PDR. ❍...

  • Page 280: I/o Port Registers

    CHAPTER 5 I/O PORT I/O Port Registers This section describes the configuration and functions of the I/O port registers. ■ Configuration of the Port Data Registers (PDR) Shown below is the configuration of the port data registers (PDR). Figure 5.2-1 Configuration of the Port Data Registers (PDR) PDR0 Initial value Access...

  • Page 281

    CHAPTER 5 I/O PORT ■ Configuration of the Data Direction Registers (DDR) Figure 5.2-2 shows the configuration of the data direction registers (DDR). Figure 5.2-2 Configuration of the Data Direction Registers (DDR) DDR0 Initial value Access Address: 000600 00000000 DDR1 Initial value Access Address: 000601...

  • Page 282

    CHAPTER 5 I/O PORT ■ Configuration of the Pull-up Resistor Control Registers (PCR) The configuration of the pull-up resistor control registers (PCR) is shown in Figure 5.2-3: Figure 5.2-3 Configuration of the Pull-up Resistor Control Registers (PCR) PCR0 Initial value Access Address: 000620 00000000...

  • Page 283

    CHAPTER 5 I/O PORT ■ Configuration of the Port Function Registers (PFR) The configuration of the port function registers (PFR) is shown in Figure 5.2-4: Figure 5.2-4 Configuration of the Port Function Registers (PFR) PFR6 Initial value Access Address: 000616 11111111 AE23 AE22...

  • Page 284

    CHAPTER 5 I/O PORT ■ Function of the Port Function Registers (PFR) The following table summarizes the initial values and functions of the PFR registers. Table 5.2-1 Functions of the Port Function Registers (PFR) (1 / 5) Initial Register name Bit name Bit value Function...

  • Page 285

    CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (2 / 5) Initial Register name Bit name Bit value Function value General-purpose port (P92) MCKE Set "1" at using memory clock and MCLK General-purpose port (P94) ASXE Set "1"...

  • Page 286

    CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (3 / 5) Initial Register name Bit name Bit value Function value 0,0,0 General-purpose port (PB0, PB1, PB2) DACK0, DEOP0 output (FR30-compatible for fly-by 0,0,1 transfer) DACK0, DEOP0 output (FR30-compatible for two- 0,1,0 cycle transfer RD timing) DACK0, DEOP0 output (FR30-compatible for two-...

  • Page 287

    CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (4 / 5) Initial Register name Bit name Bit value Function value DACK0 output active L AKH0 DACK0 output active H DACK1 output active L AKH1 DACK1 output active H General-purpose port (PB5)/DEOP1 output PFRB2 PPE1...

  • Page 288

    CHAPTER 5 I/O PORT Table 5.2-1 Functions of the Port Function Registers (PFR) (5 / 5) Initial Register name Bit name Bit value Function value General-purpose port (P67, P66)/address output (A23, A22) C I/F, SCL1, SDA1 I/O PFR61 Be sure to set "0". 000617 TEST0 Test function.

  • Page 289: Chapter 6 16-bit Reload Timer

    CHAPTER 6 16-BIT RELOAD TIMER This chapter describes the 16-bit reload timer, the configuration and functions of registers, and 16-bit reload timer operation. 6.1 Overview of the 16-bit Reload Timer 6.2 16-bit Reload Timer Registers 6.3 16-bit Reload Timer Operation 6.4 Operating States of the Counter 6.5 Precautions on Using the 16-bit Reload Timer...

  • Page 290: Overview Of The 16-bit Reload Timer

    CHAPTER 6 16-BIT RELOAD TIMER Overview of the 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating an internal count clock, and a control register. ■ Overview of the 16-bit Reload Timer The 16-bit reload timer consists of a 16-bit down counter, a 16-bit reload register, a prescaler for creating an internal count clock, and a control register.

  • Page 291: 16-bit Reload Timer Registers

    CHAPTER 6 16-BIT RELOAD TIMER 16-bit Reload Timer Registers This section describes the configuration and functions of the registers used by the 16- bit reload timer. ■ 16-bit Reload Timer Registers Figure 6.2-1 16-bit Reload Timer Registers CSL1 CSL0 MOD2 MOD1 Control status register (TMCSR) MOD0 RELD INTE...

  • Page 292: Control Status Register (tmcsr)

    CHAPTER 6 16-BIT RELOAD TIMER 6.2.1 Control Status Register (TMCSR) The control status register (TMCSR) controls the operating modes and interrupts of the 16-bit timer. ■ Bit Configuration of the Control Status Register (TMCSR) Figure 6.2-2 Bit Configuration of the Control Status Register (TMCSR) Initial value --XX0000 Address: 00004E...

  • Page 293

    CHAPTER 6 16-BIT RELOAD TIMER Table 6.2-1 Count Sources Set Using the CSL Bits CSL1 CSL0 Clock source (φ: Machine clock) Internal clock φ/2 (ch.0 to ch.2) Internal clock φ/2 (ch.0 to ch.2) Internal clock φ/2 (ch.0 to ch.2) External clock (event) (ch.0 to ch.2) Note: The minimum pulse width required for an external clock is 2T (T: Peripheral clock machine cycle).

  • Page 294

    CHAPTER 6 16-BIT RELOAD TIMER Table 6.2-3 MOD2,MOD1, and MOD0 Bits Setting Method (in Selecting Event Count Mode) MOD2 MOD1 MOD0 Valid edge or level External event (Rising edge) External event (Falling edge) External event (Both edges) Note: x in this table represents any value. Reload of external event is generated by underflow and software trigger.

  • Page 295: 16-bit Timer Register (tmr:tmr2 To Tmr0)

    CHAPTER 6 16-BIT RELOAD TIMER 6.2.2 16-bit Timer Register (TMR:TMR2 to TMR0) The 16-bit timer register (TMR:TMR2 to TMR0) is a register to which the count value of the 16-bit timer can be read. The initial value is undefined. Be sure to read this register using a 16-bit data transfer instruction. ■...

  • Page 296: 16-bit Reload Register (tmrlr:tmrlr2 To Tmrlr0)

    CHAPTER 6 16-BIT RELOAD TIMER 6.2.3 16-bit Reload Register (TMRLR:TMRLR2 to TMRLR0) The 16-bit reload register (TMRLR:TMRLR2 to TMRLR0) holds the initial value of a counter. The initial value is undefined. Be sure to read this register using a 16-bit data transfer instruction. ■...

  • Page 297: 16-bit Reload Timer Operation

    CHAPTER 6 16-BIT RELOAD TIMER 16-bit Reload Timer Operation This section describes the following operations of the 16-bit reload timer: • Internal clock operation • Underflow operation ■ Internal Clock Operation If the timer operates with a divide-by clock of the internal clock, one of the clocks created by dividing the machine clock by 2, 8, or 32 can be selected as the clock source.

  • Page 298

    CHAPTER 6 16-BIT RELOAD TIMER ■ Underflow Operation An underflow is an event in which the counter value changes from 0000 to FFFF . Thus, an underflow occurs at the count of [Reload register setting value + 1]. If the RELD bit of the control status register (TMCSR) is set to "1" when an underflow occurs, the contents of the 16-bit reload register (TMRLR) are loaded and the count operation is continued.

  • Page 299: Operating States Of The Counter

    CHAPTER 6 16-BIT RELOAD TIMER Operating States of the Counter The counter state is determined by the CNTE bit of the control status register (TMCSR) and the WAIT signal, which is an internal signal. The states that can be set including the stop state, when CNTE=0 and WAIT=1 (STOP state);...

  • Page 300: Precautions On Using The 16-bit Reload Timer

    CHAPTER 6 16-BIT RELOAD TIMER Precautions on Using the 16-bit Reload Timer This section contains precautions on using the 16-bit reload timer. ■ Precautions on Using the 16-bit Reload Timer ❍ Internal prescaler The internal prescaler is enabled if a trigger (software or external trigger) is applied while bit1 (timer enable: CNTE) of the control status register (TMCSR) is set to "1".

  • Page 301: Chapter 7 Ppg Timer

    CHAPTER 7 PPG TIMER This chapter describes the PPG timer, register configurations and functions, and PPG timer operation. The chapter also provides a block diagram of the PPG timer. 7.1 Overview of PPG Timer 7.2 Block Diagram of PPG Timer 7.3 Registers of PPG Timer 7.4 PPG Operation 7.5 One-shot Operation...

  • Page 302: Overview Of Ppg Timer

    CHAPTER 7 PPG TIMER Overview of PPG Timer The PPG timer can generate PWM wave forms with great precision and efficiency. The MB91301 series has four built-in channels for the PPG timers. ■ Features of PPG Timer • Each channel consists of the following elements: •...

  • Page 303: Block Diagram Of Ppg Timer

    CHAPTER 7 PPG TIMER Block Diagram of PPG Timer Figure 7.2-1 shows the block diagram of an entire PPG timer. Figure 7.2-2 shows the block diagram of one channel of the PPG timer. ■ Block Diagram of the Entire PPG Timer Figure 7.2-1 Block Diagram of the Entire PPG Timer TRG input 16-bit reload timer ch.0...

  • Page 304

    CHAPTER 7 PPG TIMER ■ Block Diagram of One Channel of the PPG Timer Figure 7.2-2 Block Diagram of One Channel of the PPG Timer PCRS PDUT Prescaler Load 1/16 1/64 16-bit down counter PPG mask Start Borrow Peripheral clock PPG output Reverse bit Interrupt...

  • Page 305: Registers Of Ppg Timer

    CHAPTER 7 PPG TIMER Registers of PPG Timer Figure 7.3-1 lists the registers of the PPG timer. ■ Register List of PPG Timer Figure 7.3-1 Register List of PPG Timer bit 15 GCN10 General control register 10 GCN20 General control register 20 PTMR0 PPG Timer register (ch.0) PCSR0...

  • Page 306: Control Status Registers (pcnh:pcnh3 To Pcnh0, Pcnl:pcnl3 To Pcnl0)

    CHAPTER 7 PPG TIMER 7.3.1 Control Status Registers (PCNH:PCNH3 to PCNH0, PCNL:PCNL3 to PCNL0) The control status register (PCNH:PCNH3 to PCNH0, PCNL:PCNL3 to PCNL0) controls the PPG timer and indicates the status of the timer. Note that some bits cannot be rewritten while the PPG timer is operating.

  • Page 307

    CHAPTER 7 PPG TIMER [bit13] MDSE: Mode selection bit This bit determines whether the PPG operation in which pulses are generated continuously or the one-shot operation in which only single pulses are generated is used. Table 7.3-2 Mode selection setting MDSE Function PPG operation (initial value)

  • Page 308

    CHAPTER 7 PPG TIMER [bit8] (Reserved) This bit is unused bit. [bit7, bit6] EGS1, EGS0: Trigger input edge selection bit This bit selects the valid edge for the activation source selected by the general control register 1. When the software trigger bit is set to "1", a software trigger is enabled regardless of the mode selected.

  • Page 309

    CHAPTER 7 PPG TIMER [bit1] (Reserved) This bit is unused bit. [bit0] OSEL: PPG output polarity specification bit This bit specifies the polarity of the PPG output. It becomes because of the combination with this bit and the PGMS bit of bit9 as shown in Table 7.3-9.

  • Page 310: Ppg Cycle Set Register (pcsr:pcsr3 To Pcsr0)

    CHAPTER 7 PPG TIMER 7.3.2 PPG Cycle Set Register (PCSR:PCSR3 to PCSR0) The PCSR:PCSR3 to PCSR0 is a buffer register for setting cycles. It has a buffer. Transfers from the buffer are performed through counter borrows. ■ Bit Configuration of PPG Cycle Set Register (PCSR:PCSR3 to PCSR0) The bit configuration of the PCSR:PCSR3 to PCSR0 is shown below.

  • Page 311: Ppg Duty Set Register (pdut:pdut3 To Pdut0)

    CHAPTER 7 PPG TIMER 7.3.3 PPG Duty Set Register (PDUT:PDUT3 to PDUT0) The PDUT:PDUT3 to PDUT0 is a buffer register for setting duties. It has a buffer. Transfers from the buffer are performed through counter borrows. ■ Bit Configuration of PPG Duty Set Register (PDUT:PDUT3 to PDUT0) The bit configuration of the PDUT:PDUT3 to PDUT0 is shown below.

  • Page 312: Ppg Timer Register (ptmr:ptmr3 To Ptmr0)

    CHAPTER 7 PPG TIMER 7.3.4 PPG Timer Register (PTMR:PTMR3 to PTMR0) The PTMR:PTMR3 to PTMR0 can be used to read the 16-bit down counter. ■ Bit Configuration of PPG Timer Register (PTMR:PTMR3 to PTMR0) The bit configuration of the PTMR (PTMR:PTMR3 to PTMR0) is shown below. Figure 7.3-5 Bit Configuration of PPG Timer Register (PTMR:PTMR3 to PTMR0) bit 15 Initial value...

  • Page 313: General Control Register 10 (gcn10)

    CHAPTER 7 PPG TIMER 7.3.5 General Control Register 10 (GCN10) The GCN10 selects the source of the PPG timer trigger input. ■ Bit Configuration of General Control Register 10 (GCN10) The bit configuration of the GCN10 is shown below. Figure 7.3-6 Bit Configuration of General Control Register 10 (GCN10) Address: 000118 TSEL[33:30] TSEL[23:20]...

  • Page 314

    CHAPTER 7 PPG TIMER [bit11 to bit8] TSEL23 to TSEL20: ch.2 trigger input selection bit These bits are ch.2 trigger input select bits. Table 7.3-12 Ch.2 Trigger Input Selection TSEL23 to TSEL20 Function EN0 bit of GCN2 EN1 bit of GCN2 EN2 bit of GCN2 (initial value) EN3 bit of GCN2 16-bit reload timer ch.0...

  • Page 315

    CHAPTER 7 PPG TIMER [bit3 to bit0] TSEL03 to TSEL00: ch.0 trigger input selection bit These bits are ch.0 trigger input select bits. Table 7.3-14 Ch.0 Trigger Input Selection TSEL03 to SEL00 ch.0 trigger input EN0 bit of GCN2 (initial value) EN1 bit of GCN2 EN2 bit of GCN2 EN3 bit of GCN2...

  • Page 316: General Control Register 20 (gcn20)

    CHAPTER 7 PPG TIMER 7.3.6 General Control Register 20 (GCN20) The GCN20 activates a start trigger through software. ■ Bit Configuration of General Control Register 20 (GCN20) The bit configuration of the GCN20 is shown below. Figure 7.3-7 Bit Configuration of General Control Register 20 (GCN20) Address: 00011B ←Attribute ←Initial value...

  • Page 317: Ppg Operation

    CHAPTER 7 PPG TIMER PPG Operation The PPG operation allows continuous pulses to be output after a start trigger is detected. The cycle and duty ratio of the output pulses can be controlled by changing the values of the PCSR and PDUT, respectively. After data is written to PCSR, be sure to write to PDUT.

  • Page 318

    CHAPTER 7 PPG TIMER ❍ When restart is enabled Figure 7.4-2 shows the timing chart of the PPG operation when trigger restart is enabled. Figure 7.4-2 Timing Chart of PPG Operation (Trigger Restart Enabled) Rising edge detected Restarted by trigger Start trigger A=T (n+1) ms...

  • Page 319: One-shot Operation

    CHAPTER 7 PPG TIMER One-shot Operation The one-shot operation allows output of a single pulse of any width through a trigger. If restart is enabled, the counter value is reloaded when the edge is detected during operation. ■ One-shot Operation ❍...

  • Page 320

    CHAPTER 7 PPG TIMER ❍ When restart is enabled Figure 7.5-2 shows the timing chart of a one-shot operation when a trigger restart is enabled. Figure 7.5-2 Timing Chart of One-shot Operation (Trigger Restart Enabled) Rising edge detected Restarted by trigger Start trigger A=T (n+1) ms...

  • Page 321: Ppg Timer Interrupt Source And Timing Chart

    CHAPTER 7 PPG TIMER PPG Timer Interrupt Source and Timing Chart This section describes interrupt sources and provides the related timing charts. ■ Interrupt Sources and Timing Chart (PPG Output: Normal Polarity) Figure 7.6-1 shows the PPG timer interrupt sources and a timing chart. A maximum time of 2.5 T (T: counter clock cycle) is required from when a start trigger is activated to when the counter value is loaded.

  • Page 322

    CHAPTER 7 PPG TIMER Figure 7.6-3 shows an example of setting PPG output to all-"H". Figure 7.6-3 Example of Setting PPG Output to all-"H" Increase duty ratio in stages. Write the same value as that set in cycle set register by compare match interrupt.

  • Page 323: Activating Multiple Channels By Using The General Control Register

    CHAPTER 7 PPG TIMER Activating Multiple Channels by Using the General Control Register You can activate multiple channels at the same time by selecting the start trigger with the GCN10. This section shows an example of how GCN20 is set to activate channels via software. ■...

  • Page 324

    CHAPTER 7 PPG TIMER ■ When the 16-bit Reload Timer is Used for Activation Specify the 16-bit reload timer as a source in GCN10 (see 3) above). Start the 16-bit reload timer instead of writing data to GCN20 in 5) above. In addition, set the control status register as follows: •...

  • Page 325: Notes On Use Of The Ppg Timer

    CHAPTER 7 PPG TIMER Notes on Use of the PPG Timer This section gives notes on using the PPG timer. ■ Precautions when Using • If the interrupt request flag set timing and clear timing are simultaneous, the flag setting operation overrides the flag clearing operation.

  • Page 326

    CHAPTER 7 PPG TIMER...

  • Page 327: Chapter 8 U-timer

    CHAPTER 8 U-TIMER This chapter describes the U-TIMER, the configuration and functions of registers, and U-TIMER operation. 8.1 Overview of the U-TIMER 8.2 U-TIMER Registers 8.3 U-TIMER Operation...

  • Page 328: Overview Of The U-timer

    CHAPTER 8 U-TIMER Overview of the U-TIMER This section provides an overview and a block diagram of the U-TIMER (16-bit timer for UART baud rate generation). ■ Overview of the U-TIMER The U-TIMER is a 16-bit timer used to generate the baud rate for the UART. Use a combination of a chip operating frequency and a reload value of the U-TIMER to specify a baud rate.

  • Page 329: U-timer Registers

    CHAPTER 8 U-TIMER U-TIMER Registers This section describes the configuration and functions of the registers used by the U- TIMER. ■ U-TIMER Registers Figure 8.2-1 shows the registers used by the U-TIMER. Figure 8.2-1 U-TIMER Registers UTIM UTIMR UTIMC ■ U-TIMER (UTIM:UTIM2 to UTIM0) Figure 8.2-2 shows the bit configuration of the U-TIMER (UTIM:UTIM2 to UTIM0).

  • Page 330

    CHAPTER 8 U-TIMER ■ U-TIMER Control Register (UTIMC:UTIMC2 to UTIMC0) Figure 8.2-4 shows the bit configuration of the U-TIMER control register (UTIMC:UTIMC2 to UTIMC0). Figure 8.2-4 Bit Configuration of the U-TIMER Control Register (UTIMC:UTIMC2 to UTIMC0) ch.0 Address: 000067 UCC1 UTIE UNDR CLKS UTST UTCR...

  • Page 331

    CHAPTER 8 U-TIMER [bit3] UNDR (UNDeR flow flag): Indicates generating underflow This bit indicates that an underflow has occurred. If the UNDR bit is set while the UTIE bit of bit4 is set to "1", an underflow interrupt occurs. The UNDR bit is cleared upon a reset or if "0" is written to it. For a read by a read-modify-write instruction, "1"...

  • Page 332

    CHAPTER 8 U-TIMER ■ Precautions on the U-TIMER Control Register (UTIMC) • In the stop state, assert the start bit UTST (started) to automatically reload data. • In the stop state, assert both the clear bit UTCR and the start bit UTST at the same time to clear the counter to "0"...

  • Page 333: U-timer Operation

    CHAPTER 8 U-TIMER U-TIMER Operation This section describes calculation of a baud rate for the U-TIMER and the timing in cascade mode. ■ Calculation of Baud Rate The UART uses the underflow flip-flop (f.f. in the block diagram) of the corresponding U-TIMER (from U-TIMER0 to UART0 or from U-TIMER1 to UART1 or from U-TIMER2 to UART2) as the clock source for baud rates.

  • Page 334

    CHAPTER 8 U-TIMER ■ Cascade Mode Channels 0 and 1 of the U-TIMER can be used in cascade mode. Figure 8.3-1 shows a sample timing chart for when UTIMR ch.0 is set to "0100 " and UTIMR ch.1 is set to "0002 ".

  • Page 335: Chapter 9 External Interrupt And Nmi Controller

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER This chapter describes the overview, the configuration and functions of registers, and operation of the external interrupt and NMI controller. 9.1 Overview of the External Interrupt and NMI Controller 9.2 External Interrupt and NMI Controller Registers 9.3 Operation of the External Interrupt and NMI Controller...

  • Page 336: Overview Of The External Interrupt And Nmi Controller

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER Overview of the External Interrupt and NMI Controller The external interrupt controller is a block that controls external interrupt requests input to NMI and INT0 to INT7. "H" level, "L" level, rising edge, or falling edge can be selected as the level of a request to be detected (except for NMI).

  • Page 337: External Interrupt And Nmi Controller Registers

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER External Interrupt and NMI Controller Registers This section describes the configuration and functions of the registers used by the external interrupt and NMI controller. ■ External Interrupt and NMI Controller Registers Figure 9.2-1 shows the registers used by the external interrupt and NMI controller. Figure 9.2-1 External Interrupt and NMI Controller Registers External interrupt enable register (ENIR)

  • Page 338: Interrupt Enable Register (enir)

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER 9.2.1 Interrupt Enable Register (ENIR) This section describes the bit configuration and function of the interrupt enable register (ENIR). ■ Interrupt Enable Register (ENIR: ENable Interrupt Request Register) Figure 9.2-2 shows the bit configuration of the interrupt enable register (ENIR) Figure 9.2-2 Bit Configuration of the Interrupt Enable Register (ENIR) Initial value Address: 000041...

  • Page 339: External Interrupt Request Register (eirr)

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER 9.2.2 External Interrupt Request Register (EIRR) This section describes the bit configuration and functions of the external interrupt Request Register EIRR. ■ External Interrupt Request Register (EIRR: External Interrupt Request Register) Figure 9.2-3 shows the bit configuration of the external interrupt Request Register (EIRR). Figure 9.2-3 Bit Configuration of the External Interrupt Request Register (EIRR) Initial value Address: 000040...

  • Page 340: External Interrupt Request Level Setting Register (elvr)

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER 9.2.3 External Interrupt Request Level Setting Register (ELVR) This section describes the bit configuration and functions of the external interrupt request level setting register (ELVR). ■ External Interrupt Request Level Setting Register (ELVR: External Level Register) Figure 9.2-4 shows the bit configuration of the external interrupt request level setting register (ELVR).

  • Page 341: Operation Of The External Interrupt And Nmi Controller

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER Operation of the External Interrupt and NMI Controller After a request level and an enable register are specified, if a request specified in the external interrupt request level setting register (ELVR) is input to the corresponding pin, this module generates an interrupt request signal to the interrupt controller.

  • Page 342

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ External Interrupt Request Level If the request level is an edge request, a pulse width of at least three machine cycles (peripheral clock machine cycles) is required to detect an edge. If the request input level is a level setting, the pulse width must be at least 3 machine cycles. Also, as long as the interrupt input pin retains the active level, the interrupt request is continuously made to the interrupt controller, even if the source register is cleared.

  • Page 343

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER Figure 9.3-4 shows the NMI request detector. Figure 9.3-4 NMI Request Detector (NMI flag) NMI request Q SX Falling edge (Stop clearing) detection STOP clear (RST, interrupt acknowledge) ■ Notes on Returning from STOP State Using External Interrupt In a STOP state, the first external interrupt signal to be input to the INT pin is input without being synchronized, enabling return from the STOP state.

  • Page 344

    CHAPTER 9 EXTERNAL INTERRUPT AND NMI CONTROLLER ■ Return Operation from STOP State The following operation is performed on the current circuit when an external interrupt is used to return from the STOP state. ● Procedure prior to STOP state transition Setting a path for an external interrupt It is necessary to set a path for inputting an external interrupt in order to release the STOP state before the device enters the STOP state.

  • Page 345: Chapter 10 Delayed Interupt Module

    CHAPTER 10 DELAYED INTERUPT MODULE This chapter describes the functions and operation of the delayed interrupt module. 10.1 Overview of the Delayed Interrupt Module 10.2 Delayed Interrupt Module Registers 10.3 Operation of the Delayed Interrupt Module...

  • Page 346: Overview Of The Delayed Interrupt Module

    CHAPTER 10 DELAYED INTERUPT MODULE 10.1 Overview of the Delayed Interrupt Module The delayed interrupt module generates an interrupt for switching tasks. Use this module to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request.

  • Page 347: Delayed Interrupt Module Registers

    CHAPTER 10 DELAYED INTERUPT MODULE 10.2 Delayed Interrupt Module Registers This section describes the configuration and functions of the registers used by the delayed interrupt module. ■ Delayed Interrupt Module Registers The delayed interrupt module includes the delayed interrupt control register (DICR). Figure 10.2-1 shows the configuration of the delayed interrupt control register (DICR).

  • Page 348: Operation Of The Delayed Interrupt Module

    CHAPTER 10 DELAYED INTERUPT MODULE 10.3 Operation of the Delayed Interrupt Module A delayed interrupt refers to an interrupt generated for switching tasks. Use this function to allow a software program to generate an interrupt request for the CPU or to clear an interrupt request.

  • Page 349: Chapter 11 Interrupt Controller

    CHAPTER 11 INTERRUPT CONTROLLER This chapter describes the overview of the interrupt controller, the configuration and functions of registers, and interrupt controller operation. It also presents an example of using the hold request cancellation request function. 11.1 Overview of the Interrupt Controller 11.2 Interrupt Controller Registers 11.3 Interrupt Controller Operation 11.4 Example of Using the Hold Request Cancellation Request Function...

  • Page 350: Overview Of The Interrupt Controller

    CHAPTER 11 INTERRUPT CONTROLLER 11.1 Overview of the Interrupt Controller The interrupt controller controls interrupt acceptance and arbitration processing. ■ Hardware Configuration of the Interrupt Controller The interrupt controller consists of the following components: • Interrupt control registers (ICR) register •...

  • Page 351

    CHAPTER 11 INTERRUPT CONTROLLER ■ Block Diagram Figure 11.1-1 shows a block diagram of the interrupt controller. Figure 11.1-1 Block Diagram of the Interrupt Controller UNMI WAKEUP (LEVEL 11111 : "1") Priority decision LEVEL4 to LEVEL0 processing HLDREQ MHALTI cancellation LEVEL request LEVEL decision...

  • Page 352: Interrupt Controller Registers

    CHAPTER 11 INTERRUPT CONTROLLER 11.2 Interrupt Controller Registers This section describes the configuration and functions of the registers used by the interrupt controller. ■ Interrupt Controller Registers Figure 11.2-1 shows the registers of the interrupt controller. Figure 11.2-1 Interrupt Controller Registers 000440 Address: ICR4...

  • Page 353

    CHAPTER 11 INTERRUPT CONTROLLER (Continued) 000460 Address: ICR4 ICR3 ICR2 ICR1 ICR0 ICR32 000461 Address: ICR4 ICR3 ICR2 ICR1 ICR0 ICR33 000462 Address: ICR4 ICR3 ICR2 ICR1 ICR0 ICR34 000463 Address: ICR4 ICR3 ICR2 ICR1 ICR0 ICR35 000464 Address: ICR4 ICR3 ICR2 ICR1...

  • Page 354: Interrupt Control Register (icr)

    CHAPTER 11 INTERRUPT CONTROLLER 11.2.1 Interrupt Control Register (ICR) An interrupt control register is provided for each of the interrupt input and sets the interrupt level of the corresponding interrupt request. ■ Bit Configuration of Interrupt Control Register (ICR) Figure 11.2-2 shows the bit configuration of the interrupt control register (ICR: Interrupt Control Register).

  • Page 355

    CHAPTER 11 INTERRUPT CONTROLLER Table 11.2-1 Correspondence between Possible Interrupt Level Setting Bits and Interrupt Levels ICR4 ICR3 ICR2 ICR1 ICR0 Interrupt level Reserved for system Maximum level that can be set (High) (Low) Interrupt disabled Note: The ICR4 bit is always "1". "0" cannot be written to it.

  • Page 356: Hold Request Cancellation Request Level Setting Register (hrcl)

    CHAPTER 11 INTERRUPT CONTROLLER 11.2.2 Hold Request Cancellation Request Level Setting Register (HRCL) The hold request cancellation request level setting register (HRCL) is a level setting register used to generate a hold request cancellation request. ■ Bit Configuration of Hold Request Cancellation Request Level Setting Register (HRCL) Figure 11.2-3 shows the bit configuration of the hold request cancellation request level setting register (HRCL).

  • Page 357: Interrupt Controller Operation

    CHAPTER 11 INTERRUPT CONTROLLER 11.3 Interrupt Controller Operation This section describes the following items regarding operation of the interrupt controller: • Priority decision • NMI • Hold request cancellation request • Return from standby mode (stop/sleep) ■ Priority Decision The interrupt controller selects the interrupt source with the highest priority from among those that exist simultaneously and outputs the interrupt level and the interrupt number of this source to the CPU.

  • Page 358

    CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (2 / 4) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal − − Operand break trap 000FFFD0 − − Step trace trap 000FFFCC −...

  • Page 359

    CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (3 / 4) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal − PPG2 ICR25 000FFF58 − PPG3 ICR26 000FFF54 − Reserved for system ICR27 000FFF50 −...

  • Page 360

    CHAPTER 11 INTERRUPT CONTROLLER Table 11.3-1 Relationship between Interrupt Sources, Interrupt Numbers, and Interrupt Levels (4 / 4) Interrupt number Default Interrupt Interrupt source Offset address of level Decimal Hexadecimal − − Reserved for system 000FFEE0 − − Reserved for system 000FFEDC −...

  • Page 361

    CHAPTER 11 INTERRUPT CONTROLLER ■ Hold Request Cancellation Request (HRCR: Hold Request Cancel Request) For an interrupt with a higher priority to be processed during CPU hold, the device that has generated the hold request must cancel the request. Set the interrupt level in the HRCL register to be used as the criterion of generating a cancellation request.

  • Page 362

    CHAPTER 11 INTERRUPT CONTROLLER ■ Return from Standby Mode (Sleep/Stop) This module implements a function that causes a return from stop mode if an interrupt request occurs. If at least one interrupt request that includes NMI occurs (with an interrupt level other than "11111 ") from the peripheral, a return request from stop mode is generated for the clock controller.

  • Page 363: Example Of Using The Hold Request Cancellation Request Function (hrcr)

    CHAPTER 11 INTERRUPT CONTROLLER 11.4 Example of Using the Hold Request Cancellation Request Function (HRCR) To allow the CPU to perform high-priority processing during DMA transfer, cancel a hold request for DMA and clear the hold state. In this example, an interrupt is used to cancel a hold request to the DMA, allowing the CPU to perform priority operations.

  • Page 364

    CHAPTER 11 INTERRUPT CONTROLLER ■ Hold Request Cancellation Request Sequence Figure 11.4-2 shows the timing chart of a hold request cancellation request. Figure 11.4-2 Timing Chart of a Hold Request Cancellation Request Bus hold Bus hold Interrupt processing (DMA transfer) Bus access request DHREQ DHACK...

  • Page 365: Chapter 12 A/d Converter

    CHAPTER 12 A/D CONVERTER This chapter describes the overview A/D converter, the configuration and functions of registers, and A/D converter operation. 12.1 Overview of the A/D Converter 12.2 A/D Converter Registers 12.3 A/D Converter Operation 12.4 Precautions on the Using A/D Converter...

  • Page 366: Overview Of The A/d Converter

    CHAPTER 12 A/D CONVERTER 12.1 Overview of the A/D Converter The A/D converter is a module that converts an analog input voltage to a digital value in the successive approximation conversion method. ■ Features The A/D converter, which converts an analog voltage input to an analog input pin (input voltage) to a digital value, has the following features: •...

  • Page 367

    CHAPTER 12 A/D CONVERTER ■ Block Diagram Figure 12.1-1 shows a block diagram of the A/D converter. Figure 12.1-1 Block Diagram of the A/D Converter AVcc AVRH AVss AVR Internal voltage generator Sample and hold circuit Sequential comparison register Data register(ADCR) Upper 8-bit COPY Data register(ADCR0 to ADCR3:8 bits)

  • Page 368: A/d Converter Registers

    CHAPTER 12 A/D CONVERTER 12.2 A/D Converter Registers This section describes the configuration and functions of the registers used by the A/D converter. ■ A/D Converter Registers Figure 12.2-1 shows the registers of the A/D converter. Figure 12.2-1 A/D Converter Registers Address: 00007A BUSY INTE...

  • Page 369: Control Status Register (adcs)

    CHAPTER 12 A/D CONVERTER 12.2.1 Control Status Register (ADCS) The control status register (ADCS) controls the A/D converter and displays its status. ■ Bit Configuration of Control Status Register (ADCS) Figure 12.2-2 shows the bit configuration of the control status register (ADCS). Figure 12.2-2 Bit Configuration of the Control Status Register (ADCS) Initial value Address: 00007A...

  • Page 370

    CHAPTER 12 A/D CONVERTER Note: Clear this bit by writing "0" to it while the A/D is stopped. This bit is initialized to "0" by a reset. For a read by a read-modify-write instruction, "1" is read. [bit13] INTE (INTerrupt Enable): Specifying interrupt by conversion termination This bit specifies enabling or disabling of interrupts when conversion is completed.

  • Page 371

    CHAPTER 12 A/D CONVERTER Notes: Since start sources change at the same time that rewriting occurs, be careful when this bit is rewritten during the A/D conversion operation. • An external pin trigger is detected at a falling edge. If this bit is rewritten to select starting due to an external trigger while the external trigger input level is set to "L", the A/D converter may be started.

  • Page 372

    CHAPTER 12 A/D CONVERTER Note: When the A/D conversion mode selection bits (MD1 and MD0) are set to "00 ", restart during A/D conversion is enabled. In this modes, software start (STS1 and STS0 = "00 ") can only be set. Restart in the following procedures.

  • Page 373

    CHAPTER 12 A/D CONVERTER [bit2, bit1, bit0] ANE2, ANE1, ANE0 (ANalog End channel set) Setting of A/D conversion end channel These bits set an A/D conversion end channel. Table 12.2-6 shows the settings for the A/D conversion end channels. Table 12.2-6 Settings for A/D Conversion End Channels ANE2 ANE1 ANE0...

  • Page 374: Data Register (adcr)

    CHAPTER 12 A/D CONVERTER 12.2.2 Data Register (ADCR) The data register (ADCR) stores the A/D conversion result. A digital value is stored as the current result of conversion. ■ Data Register (ADCR) Figure 12.2-3 shows the bit configuration of the data register (ADCR). Figure 12.2-3 Bit Configuration of the Data Register (ADCR) Initial value Address: 000078...

  • Page 375: Conversion Result Register (adcr0 To Adcr3)

    CHAPTER 12 A/D CONVERTER 12.2.3 Conversion result register (ADCR0 to ADCR3) The conversion result registers (ADCR0 to ADCR3) store the results of A/D conversion. The register stores the digital value resulting from conversion of the corresponding channel. ■ Conversion Result Register (ADCR0 to ADCR3) Figure 12.2-4 shows the bit configurations of the conversion result registers (ADCR0 to ADCR3).

  • Page 376: A/d Converter Operation

    CHAPTER 12 A/D CONVERTER 12.3 A/D Converter Operation The A/D converter operates using the successive approximation conversion method and has a 10-bit resolution. Upon completion of each conversion, this A/D converter stores the upper eight bits in the 8-bit conversion result register (ADCR0 to ADCR3) for the corresponding channel. To read a conversion result, read the corresponding conversion result register (ADCR0 to ADCR3).

  • Page 377

    CHAPTER 12 A/D CONVERTER ■ Continuous Conversion Mode This mode sequentially converts the analog input defined by the ANS and ANE bits, returns to the analog input of ANS after performing the conversion up to the end channel defined by the ANE bit, and continues the A/D conversion operation.

  • Page 378: Precautions On The Using A/d Converter

    CHAPTER 12 A/D CONVERTER 12.4 Precautions on the Using A/D Converter This section contains precautions on using the A/D converter. ■ Precautions on Using the A/D Converter To start the A/D converter using an external trigger or an internal timer, set the A/D start source bits (STS1 and STS0) of the ADCS register.

  • Page 379: Chapter 13 Uart

    CHAPTER 13 UART This chapter describes the overview of the UART, the configuration and functions of registers, and UART operation. 13.1 Overview of the UART 13.2 UART Registers 13.3 UART Operation 13.4 Example of Using the UART 13.5 Example of Setting Baud Rates and U-TIMER Reload Values...

  • Page 380: Overview Of The Uart

    CHAPTER 13 UART 13.1 Overview of the UART The UART is a serial I/O port used to perform asynchronous (start-stop synchronization) communication and CLK synchronous communication. The MB91301 series has three UART channels. ■ Features of the UART The UART has the following features: •...

  • Page 381

    CHAPTER 13 UART ■ Block Diagram Figure 13.1-1 shows a block diagram of the UART. Figure 13.1-1 Block Diagram of the UART Control signal Receive interrupt (to CPU) SCK (clock) Send clock From U-TIMER Clock Receive clock selection Send interrupt circuit (to CPU) External clock...

  • Page 382: Uart Registers

    CHAPTER 13 UART 13.2 UART Registers This section describes the configuration and functions of the registers used by the UART. ■ UART Registers Figure 13.2-1 shows the configuration of the UART registers and Figure 13.2-2 lists the UART registers. Figure 13.2-1 Configuration of UART Registers bit15 bit8 bit7 bit0...

  • Page 383: Serial Mode Register (smr)

    CHAPTER 13 UART 13.2.1 Serial Mode Register (SMR) The serial mode register (SMR) specifies the UART operating mode. Set an operating mode while operation is stopped. Do not write to this register while operation is in progress. ■ Bit Configuration of Serial Mode Register (SMR) Figure 13.2-3 shows the bit configuration of the serial mode register (SMR).

  • Page 384

    CHAPTER 13 UART [bit3] CS0 (Clock Select): Selection of operating clock This bit selects the UART operating clock. Table 13.2-2 shows the selection of the operating clock. Table 13.2-2 Function for Selection of Operation Clock Function Built-in timer (U-TIMER) [initial value] External clock [bit2] (Reserved) This bit is unused.

  • Page 385: Serial Control Register (scr)

    CHAPTER 13 UART 13.2.2 Serial Control Register (SCR) The serial control register (SCR) controls the transfer protocol that is used for serial communication. This section describes the configuration and functions of the serial control register (SCR). ■ Bit Configuration of Serial Control Register (SCR) Figure 13.2-4 shows the bit configuration of the serial control register (SCR).

  • Page 386

    CHAPTER 13 UART [bit5] SBL (Stop Bit Length): Specifying of stop bit length This bit specifies the stop bit length, which marks the end of a frame in asynchronous (start- stop synchronization) communication. Table 13.2-6 shows specifying of the stop bit length. Table 13.2-6 Function for specifying of Stop Bit Length Function 1 stop bit...

  • Page 387

    CHAPTER 13 UART [bit1] RXE (Receiver Enable): Controlling of receive operation This bit controls the UART receive operation. Table 13.2-9 shows controlling of the receive operation. Table 13.2-9 Function for Controlling of Recive Operation Function Disables receive operation. [initial value] Enables receive operation.

  • Page 388: Serial Input Data Register (sidr)/serial Output Data Register (sodr)

    CHAPTER 13 UART 13.2.3 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) These registers are data buffer registers for receiving and sending. ■ Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) Figure 13.2-5 shows the bit configurations of the serial input data register (SIDR) and the serial output data register (SODR).

  • Page 389: Serial Status Register (ssr)

    CHAPTER 13 UART 13.2.4 Serial Status Register (SSR) The serial status register (SSR) consists of flags that indicate the operation state of the UART. This section describes the configuration and functions of the serial status register (SSR). ■ Bit Configuration of Serial Status Register (SSR) Figure 13.2-6 shows the bit configuration of the serial status register (SSR) Figure 13.2-6 Bit Configuration of the Serial Status Register (SSR) Initial value...

  • Page 390

    CHAPTER 13 UART [bit5] FRE (FRaming Error): Presence or absence of framing error This bit, which is an interrupt request flag, is set when a framing error occurs during reception. Table 13.2-13 shows the presence or absence of the framing error. Table 13.2-13 Presence or Absence of Framing Error Function No framing error has occurred.

  • Page 391

    CHAPTER 13 UART [bit2] BDS (Bit Direction Select): Transfer direction selection This bit is transfer direction selection bit. Table 13.2-16 shows the transfer direction selection. Table 13.2-16 Transfer Direction Selection Function Transfer starting from the least significant bit. (LSB) [initial value] Transfer starting from the most significant bit.

  • Page 392

    CHAPTER 13 UART Note: Send interrupt sources include send requests due to TDRE.

  • Page 393: Uart Operation

    CHAPTER 13 UART 13.3 UART Operation The UART has two operating modes: asynchronous (start-stop synchronization) mode and CLK synchronous mode. Asynchronous (start-stop synchronization) mode consists of normal and multiprocessor modes. This section describes the operation of these operating modes. ■ UART Operating Modes The UART has the operating modes shown in Table 13.3-1.

  • Page 394: Asynchronous (start-stop Synchronization) Mode

    CHAPTER 13 UART 13.3.1 Asynchronous (Start-stop Synchronization) Mode When the UART is used in operating mode 0 (normal mode) or operating mode 1 (multiprocessor mode), the asynchronous transfer method is used. ■ Transfer Data Format UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.3-1 shows the data format.

  • Page 395: Clk Synchronous Mode

    CHAPTER 13 UART 13.3.2 CLK Synchronous Mode If the UART is used in operating mode 2, the clock synchronous transfer method is used. ■ Transfer Data Format The UART handles only data in the NRZ (Non Return to Zero) format. Figure 13.3-2 shows the relationship between send and receive clocks and data.

  • Page 396

    CHAPTER 13 UART ■ Initialization The following shows the setting values of the control registers required to use CLK synchronous mode. • SMR register • MD1, MD0:"10 " • Specifies the clock input. • SCKE: Set to "1" for an internal timer and to "0" for an external clock. •...

  • Page 397: Occurrence Of Interrupts And Timing For Setting Flags

    CHAPTER 13 UART 13.3.3 Occurrence of Interrupts and Timing for Setting Flags The UART has five flags and two interrupt sources. The five flags are PE, ORE, FRE, RDRF, and TDRE. PE means parity error, ORE means overrun error, and FRE means framing error. These flags are set when an error occurs during reception and are then cleared when "0"...

  • Page 398

    CHAPTER 13 UART ❍ Receive operation in Mode 1 The ORE, FRE, and RDRF flags are set when the last stop bit is detected after a receive transfer is completed, causing an interrupt request to be generated for the CPU. The data indicating an address or the data in last 9th bit is invalid because the length of data that can be received is 8 bits.

  • Page 399

    CHAPTER 13 UART ❍ Send operation in modes 0, 1, and 2 TDRE is cleared when data is written to the SODR register. This bit is set when data is transferred to the internal shift register and the next data can be written, causing an interrupt request to be generated for the CPU.

  • Page 400: Example Of Using The Uart

    CHAPTER 13 UART 13.4 Example of Using the UART This section provides an example of using the UART. Mode 1 is used if more than one slave CPU is connected to a single host CPU. ■ Example of Using the UART Figure 13.4-1 shows an example of constructing a system using mode 1.

  • Page 401

    CHAPTER 13 UART Figure 13.4-2 Communication Flowchart in Mode 1 (Host CPU) START Set transfer mode to "1". Set data used to select slave CPUs in D0 to D7, set "1" in A/D, and transfer one byte. Set "0" in A/D. Enable receive operation.

  • Page 402: Example Of Setting Baud Rates And U-timer Reload Values

    CHAPTER 13 UART 13.5 Example of Setting Baud Rates and U-TIMER Reload Values This section provides an example of setting baud rates and U-TIMER reload values. ■ Example of Setting Baud Rates and U-TIMER Reload Values Table 13.5-1 shows setting values to be used in asynchronous (start-stop synchronization) mode.

  • Page 403: Chapter 14 Dma Controller (dmac)

    CHAPTER 14 DMA CONTROLLER (DMAC) This chapter describes the overview of the DMA controller (DMAC), the configuration and functions of registers, and DMAC operation. 14.1 Overview of the DMA Controller (DMAC) 14.2 DMA Controller (DMAC) Registers 14.3 DMA Controller (DMAC) Operation 14.4 Operation Flowcharts 14.5 Data Bus 14.6 DMA External Interface...

  • Page 404: Overview Of The Dma Controller (dmac)

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.1 Overview of the DMA Controller (DMAC) The DMA controller (DMAC) is a module that implements DMA (Direct Memory Access) transfer on FR family devices. When this module is used to control DMA transfer, various kinds of data can be transferred at high speed by bypassing the CPU, enhancing system performance.

  • Page 405

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Block Diagram Figure 14.1-1 is a block diagram of the DMA controller (DMAC). Figure 14.1-1 Block Diagram of the DMA Controller (DMAC) Counter DMA activation Buffer source DMA transfer request to Peripheral activation request/stop input selection circuit the bus controller &...

  • Page 406: Dma Controller (dmac) Registers

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.2 DMA Controller (DMAC) Registers This section describes the configuration and functions of the registers used by the DMA controller (DMAC). ■ DMA Controller (DMAC) Registers Figure 14.2-1 shows the registers of the DMA controller (DMAC). Figure 14.2-1 DMA Controller (DMAC) Registers bit 31 ch.0...

  • Page 407

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Notes on Setting Registers When the DMA controller (DMAC) is set, some bits need to be set while DMA is stopped. If they are set while DMA is in progress (during transfer), correct operation cannot be guaranteed. An asterisk following a bit when its function is described later indicates that the operation of the bit is affected if it is set during DMAC transfer.

  • Page 408: Control/status Registers A (dmaca0 To Dmaca4)

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.1 Control/Status Registers A (DMACA0 to DMACA4) Control/status registers A (DMACA0 to DMACA4) control the operation of the DMAC channels. There is a separate register for each channel. This section describes the configuration and functions of control/status registers A (DMACA0 to DMACA4).

  • Page 409

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit30] PAUS (PAUSe): Temporary stop instruction This bit temporarily stops DMA transfer on the corresponding channel. If this bit is set, DMA transfer is not performed before this bit is cleared again (While DMA is stopped, the DSS bits are "1XX ").

  • Page 410

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit28 to bit24] IS4 to IS0 (Input Select): Transfer source selection These bits select the source of a transfer request. Note that the software transfer request by the STRG bit function is always valid regardless of the setting of these bits. As listed in Table 14.2-4.

  • Page 411

    CHAPTER 14 DMA CONTROLLER (DMAC) Notes: • If DMA start resulting from an interrupt from a peripheral function is set (IS=1XXXX ), disable interrupts from the selected peripheral function with the ICR register. • If demand transfer mode is selected, only IS[4:0]=01110 , 01111 can be set.

  • Page 412

    CHAPTER 14 DMA CONTROLLER (DMAC) • When reset: Initialized to "0000 ". • These bits are readable and writable. Note: This function is not supported by the MB91301 series. Any data written is ignored. Normally, write "0000 ". [bit19 to bit16] BLK3 to BLK0 (BLocK size): Block size specification These bits specify the block size for block transfer on the corresponding channel.

  • Page 413: Control/status Registers B (dmacb0 To Dmacb4)

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.2 Control/Status Registers B (DMACB0 to DMACB4) Control/status registers B (DMACB0 to DMACB4) control the operation of each DMAC channel and exist independently for each channel. This section describes the configuration of control/status registers B (DMACB0 to DMACB4) and their functions.

  • Page 414

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit29, bit28] MOD (MODe) : Transfer mode setting These bits are the transfer mode setting bits and set the operating mode of the corresponding channel. Table 14.2-9 shows the settings for the transfer modes. Table 14.2-9 Settings for Transfer Modes Function Block/step transfer mode (initial value) Burst transfer mode...

  • Page 415

    CHAPTER 14 DMA CONTROLLER (DMAC) Table 14.2-11 shows the function of the transfer source address count mode specification. Table 14.2-11 Function of Transfer Source Address Count Mode Specification SADM Function Increments the transfer source address. (initial value) Decrements the transfer source address. •...

  • Page 416

    CHAPTER 14 DMA CONTROLLER (DMAC) Table 14.2-13 shows the function of the transfer count register reload specification. Table 14.2-13 Function of Transfer Count Register Reload Specification DTCR Function Disables transfer count register reloading (initial value) Enables transfer count register reloading. •...

  • Page 417

    CHAPTER 14 DMA CONTROLLER (DMAC) Table 14.2-15 shows the function of the transfer destination address register reload specification. Table 14.2-15 Function of Transfer Destination Address Register Reload Specification DADR Function Disables transfer destination address register reloading. (initial value) Enables transfer destination address register reloading. •...

  • Page 418

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit18 to bit16] DSS2 to DSS0 (Dma Stop Status): Transfer stop source indication These bits indicate a code (end code) of 3 bits that indicates the source of stopping or termination of DMA transfer on the corresponding channel. For a list of end codes, see Table 14.2-18.

  • Page 419

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit7 to bit0] DASZ (Des Addr count SiZe):Transfer destination address count size specification These bits specify the increment or decrement width for the transfer destination address (DMADA) of the corresponding channel in each transfer operation. The value set by these bits becomes the address increment/decrement width for each transfer unit.

  • Page 420: Transfer Source/transfer Destination Address Setting Registers (dmasa0 To Dmasa4/dmada0 To Dmada4)

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.3 Transfer Source/Transfer Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to DMADA4) The transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4) control the operation of the DMAC channels. There is a separate register for each channel. This section describes the configuration and functions of the transfer source/transfer destination address setting registers (DMASA0 to DMASA4/DMADA0 to DMADA4).

  • Page 421

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit31 to bit0] D (DMA Destination Addr): Transfer destination address setting These bits set the transfer destination address. If DMA transfer is activated, data in this register is stored in the counter buffer of the DMA- dedicated address counter and then the address is counted according to the settings for the transfer operation.

  • Page 422: Dmac All-channel Control Register (dmacr)

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.4 DMAC All-Channel Control Register (DMACR) The DMAC all-channel control register (DMACR) controls the operation of all five DMAC channels. Be sure to access this register using byte length. This section describes the configuration and functions of the DMAC all-channel control register (DMACR).

  • Page 423

    CHAPTER 14 DMA CONTROLLER (DMAC) [bit28] PM01 (Priority mode ch.0,ch.1 robine): Channel priority rotation This bit is set to alternate priority for each transfer between ch.0 and ch.1. Table 14.2-22 shows the function of the channel Priority rotation. Table 14.2-22 Function of Channel Priority Rotation PM01 Function Fixes the priority.

  • Page 424: Other Functions

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.2.5 Other Functions The MB91301 series has the DACK, DEOP, and DREQ pins, which can be used for external transfer. These pins can also be used as general-purpose ports. ■ Function of the DACK, DEOP, and DREQ Pins To use the DACK, DEOP, or DREQ pins for external transfer, a switch must be made from the port function to the DMA pin function.

  • Page 425: Dma Controller (dmac) Operation

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3 DMA Controller (DMAC) Operation A DMA controller (DMAC) is built into all FR family devices. The FR family DMAC is a multi-functional DMAC that controls data transfer at high speed without the use of CPU instructions.

  • Page 426

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Transfer Type ❍ 2-cycle transfer (normal transfer) The DMA controller operates using a read operation and a write operation as its unit of operation. Data is read from an address in the transfer source register and then written to another address in the transfer destination register.

  • Page 427

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Transfer Count and Transfer End ❍ Transfer count The transfer count register is decremented (-1) after each block transfer unit is completed. When the transfer count register becomes "0", counting for the specified transfer ends, and the transfer stops with the end code displayed or is reactivated *.

  • Page 428: Setting A Transfer Request

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.1 Setting a Transfer Request The following three types of transfer requests are provided to activate DMA transfer: • External transfer request pin • Built-in peripheral request • Software request Software requests can always be used regardless of the settings of other requests. ■...

  • Page 429

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Software Request A transfer request is generated by writing to the trigger bit of a register (STRG of DMACA). The software request is independent of the external transfer request pin and built-in peripheral request and can always be caused. If a software request occurs together with a start (transfer enable) request, the transfer is started by immediate output of a DMA transfer request to the bus controller.

  • Page 430: Transfer Sequence

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.2 Transfer Sequence The transfer type and the transfer mode that determine, for example, the operation sequence after DMA transfer has started can be set independently for each channel (Settings for TYPE[1:0] and MOD[1:0] of DMACB). ■...

  • Page 431

    CHAPTER 14 DMA CONTROLLER (DMAC) Figure 14.3-1 Example of Burst Transfer for a Start on an External Pin Rising Edge, Number of Blocks =1, and Transfer Count = 4 Transfer request ( edge) Bus operation Transfer count Transfer end ❍ Burst fly-by transfer A burst fly-by transfer has the same features as a 2-cycle transfer except that the transfer area can only be external areas, and the transfer unit is read (memory -->...

  • Page 432

    CHAPTER 14 DMA CONTROLLER (DMAC) Table 14.3-3 shows the specifiable transfer addresses (demand transfer 2-cycle transfer). Table 14.3-3 Specifiable Transfer Addresses (Demand Transfer 2-cycle Transfer) Transfer source address Direction Transfer destination addressing → External area External area → External area Built-in I/O →...

  • Page 433

    CHAPTER 14 DMA CONTROLLER (DMAC) • If a transfer request for another channel with a higher priority is received during transfer, the channel is switched after the transfer is stopped and then restarted. Priority in a step transfer is valid only if transfer requests occur simultaneously. [Block transfer] If any value other than "1"...

  • Page 434: General Aspects Of Dma Transfer

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.3 General Aspects of DMA Transfer This section describes the block size for DMA transfers and the reload operation. ■ Block Size • The unit and increment for transfer data is a set of (the number set in the block size specification register x data width) data.

  • Page 435

    CHAPTER 14 DMA CONTROLLER (DMAC) ❍ Special examples of operating mode and the reload operation • If transfer is performed in continuous transfer mode by external pin input level detection and transfer count register reloading is used, transfer continues by reloading even though transfer ends during continuous input.

  • Page 436: Addressing Mode

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.4 Addressing Mode Specify the transfer destination/transfer source address independently for each transfer channel. ■ Address Register Specifications The following two methods are provided to specify an address register. The method specified depends on the transfer sequence. •...

  • Page 437: Data Types

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.5 Data Types Select the data length (data width) transferred in one transfer operation from the followings: • Byte • Halfword • Word ■ Data Length (Data Width) Since the word boundary specification is also observed in DMA transfer, different low-order bits are ignored if an address with a different data length is specified for the transfer destination/ transfer source address.

  • Page 438: Transfer Count Control

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.6 Transfer Count Control Specify the transfer count within the range of the maximum 16-bit length (1 to 65536). ■ Transfer Count Control Set the transfer count value in the transfer count register (DTC of DMACA). The register value is stored in the temporary storage buffer when the transfer starts and is decremented by the transfer counter.

  • Page 439: Cpu Control

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.7 CPU Control When a DMA transfer request is accepted, DMA issues a transfer request to the bus controller. The bus controller passes the right to use the internal bus to DMA at a break in bus operation and DMA transfer starts.

  • Page 440: Hold Arbitration

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.8 Hold Arbitration When a device is operating in external bus extended mode, an external hold function can be used. The relationship between external hold requests and DMA transfer requests by this module when the hold function can be used is described below. ■...

  • Page 441: Operation From Starting To End/stopping

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.9 Operation from Starting to End/Stopping Starting of DMA transfer is controlled independently for each channel, but before transfer starts, the operation of all channels needs to be enabled. This section describes operation from starting to end/stopping. ■...

  • Page 442

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Clearing Peripheral Interrupts by DMA This DMA has a function that clears peripheral interrupts. This function works when peripheral interrupt is selected as the DMA start source (when IS[4:0]=1XXXX Peripheral interrupts are cleared only for the set start sources. That is, only the peripheral functions set by IS[4:0] are cleared.

  • Page 443

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Operation End/Stopping The end of DMA transfer is controlled independently for each channel. It is also possible to disable operation for all channels at once. ❍ Transfer end If reloading is disabled, transfer is stopped, "Normal end" is displayed as the end code, and all transfer requests are disabled after the transfer count register becomes "0"...

  • Page 444

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Occurrence of an Address Error If inappropriate addressing, as shown below in parenthesis, occurs in an addressing mode, an address error is detected (if an overflow or underflow occurs in the address counter when a 32- bit address is specified).

  • Page 445: Dmac Interrupt Control

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.10 DMAC Interrupt Control Independent of peripheral interrupts that become transfer requests, interrupts can also be output for each DMAC channel. ■ DMAC Interrupt Control The following interrupts can be output for each DMAC channel: •...

  • Page 446: Channel Selection And Control

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.11 Channel Selection and Control Up to five channels can be simultaneously set as transfer channels. In general, an independent function can be set for each channel. ■ Priority among Channels Since DMA transfer is possible only on one channel at a time, priority must be set for the channels.

  • Page 447

    CHAPTER 14 DMA CONTROLLER (DMAC) Figure 14.3-5 Timing Example in Rotation Mode ch.0 transfer request ch.1 transfer request Bus operation Transfer ch ch.1 ch.0 ch.1 ch.0 ch.0 transfer end ch.1 transfer end ■ Channel Group The order of priority is set as shown in the following table. Table 14.3-8 Unit for Selecting the Order of Priority MODE Priority...

  • Page 448: Supplement On External Pin And Internal Operation Timing

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.3.12 Supplement on External Pin and Internal Operation Timing This section provides supplementary information about external pins and internal operation timing. ■ Minimum Effective Pulse Width of the DREQ Pin Input Only channels 0 and 1 are applicable for the MB91301 series. In all transfer modes for burst, step, block, and demand transfers, the minimum width required is five system clock cycles (5 cycles of external bus clock CLKT).

  • Page 449

    CHAPTER 14 DMA CONTROLLER (DMAC) Figure 14.3-6 Negate Timing Example of the DREQ Pin Input for 2-cycle External Transfer --> Internal Transfer External bus clock DREQn DACKn Perform the negation process within the range indicated by the arrows. Delaying the negation timing beyond the point indicated by the symbol may result in one extra transfer.

  • Page 450

    CHAPTER 14 DMA CONTROLLER (DMAC) Figure 14.3-7 Negate Timing Example of the DREQ Pin Input for Fly-by (Timing to IORD Pin) Transfer External bus clock DREQn DACKn IORD Perform the negation process within the range indicated by the arrows. Delaying the negation timing beyond the point indicated by the symbol may result in one extra transfer.

  • Page 451

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Timing of the DEOP Pin Output • The DEOP output of this DMA indicates that DMA transfer for the specified number of times of the accepted channel has been completed. • DEOP output is output when access to an external area of the last transfer block starts. Thus, if any value other than "1"...

  • Page 452: Operation Flowcharts

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.4 Operation Flowcharts This section contains operation flowcharts for the following transfer modes: • Block transfer • Burst transfer • Demand transfer ■ Block Transfer Figure 14.4-1 shows the operation flowchart for block transfer. Figure 14.4-1 Operation Flowchart for Block Transfer DMA stop DENB=>0 DENB=1...

  • Page 453

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Burst Transfer Figure 14.4-2 shows the operation flowchart for burst transfer. Figure 14.4-2 Operation Flowchart for Burst Transfer DMA stop DENB=>0 DENB=1 Activation request wait Reload enable Load the initial address, transfer count, and number of blocks Calculate the address for transfer source address access...

  • Page 454

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Demand Transfer Figure 14.4-3 shows the operation flowchart for demand transfer. Figure 14.4-3 Operation Flowchart for Demand Transfer DMA stop DENB=>0 DENB=1 None Activation request wait Reload enable Activation request Load the initial address, transfer count, and number of blocks Calculate the address for...

  • Page 455: Data Bus

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.5 Data Bus This section shows the flow of data during 2-cycle transfer and fly-by transfer. ■ Flow of Data during 2-Cycle Transfer Figure 14.5-1 shows examples of six types of transfer during 2-cycle transfer. Figure 14.5-1 Examples of 2-Cycle Transfer (Continued on Next Page) External area =>...

  • Page 456

    CHAPTER 14 DMA CONTROLLER (DMAC) (Continued) Built-in I/O area => internal RAM area transfer MB91301 MB91301 DMAC DMAC Write cycle Read cycle I-bus I-bus X-bus X-bus Bus controller Bus controller D-bus D-bus Data buffer Data buffer F-bus F-bus Internal RAM area => external area transfer MB91301 MB91301 DMAC...

  • Page 457

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Flow of Data during Fly-By Transfer Figure 14.5-2 shows examples of two types of transfer during fly-by transfer. Figure 14.5-2 Examples of Fly-By Transfer Fly-by transfer (memory to I/O) MB91301 DMAC Memory read by RD or CSn Read cycle I-bus X-bus...

  • Page 458: Dma External Interface

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.6 DMA External Interface This section provides operation timing charts for the DMA external interface. ■ DMA External Interface Pins DMA channels 0, 1 have the following DMA-dedicated pins (DREQ, DACK, and DEOP): • DREQ: DMA transfer request input pin for demand transfer. A transfer is requested with an input.

  • Page 459: Input Timing Of The Dreqx Pin

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.6.1 Input Timing of the DREQx Pin The DREQx pin is a DMA start request signal. If the pin is also used as a port, enable the DREQ input using the PFR register. This section shows the input timing of the DREQx pin.

  • Page 460

    CHAPTER 14 DMA CONTROLLER (DMAC) ■ Timing of Demand Transfer For demand transfer, set the DMA start source to level detection. Although there is no rule for starting, synchronize with RD/WRn of the DMA transfer when stopping a transfer. The sense timing is the rise of MCLK in the final external access.

  • Page 461: Fr30 Compatible Mode Of Dack

    CHAPTER 14 DMA CONTROLLER (DMAC) 14.6.2 FR30 Compatible Mode of DACK FR30 compatible mode of DACK makes the DACK timing identical to the timing of DMA used in FR30 devices. This section provides the timing charts for the DACK pin in FR30 compatible mode for the following examples of transfer mode setting: •...

  • Page 462

    CHAPTER 14 DMA CONTROLLER (DMAC) ❍ Fly-by transfer mode Figure 14.6-4 shows the timing chart in fly-by transfer mode. Figure 14.6-4 Timing Chart in Fly-By Transfer Mode DQMUU/DQMUL WR/WRn IORD IOWR DACK (AKxx=111 Same timing as the chip select DACK (AKxx=001 DACK (AKxx=010 Fly-by transfer setting disabled DACK (AKxx=011...

  • Page 463: Chapter 15 Bit Search Module

    CHAPTER 15 BIT SEARCH MODULE This chapter describes the overview of the bit search module, the configuration and functions of registers, and bit search module operation. 15.1 Overview of the Bit Search Module 15.2 Bit Search Module Registers 15.3 Bit Search Module Operation...

  • Page 464: Overview Of The Bit Search Module

    CHAPTER 15 BIT SEARCH MODULE 15.1 Overview of the Bit Search Module The bit search module searches for "0", "1", or any points of change for data written to the input register and then returns the detected bit locations. ■ Block Diagram of the Bit Search Module Figure 15.1-1 is a block diagram of the bit search module.

  • Page 465: Bit Search Module Registers

    CHAPTER 15 BIT SEARCH MODULE 15.2 Bit Search Module Registers This section describes the registers of the bit search module. ■ Bit Search Module Registers Figure 15.2-1 Bit Search Module Register 0 detection data register (BSD0) 1 detection data register (BSD1) Change point detection data register (BSDC) Detection result register (BSRR) ■...

  • Page 466

    CHAPTER 15 BIT SEARCH MODULE ❍ Reading • Save data of the internal state of the bit search module is read. This register is used to save and restore the original state when the bit search module is used by, for example, an interrupt handler.

  • Page 467: Bit Search Module Operation

    CHAPTER 15 BIT SEARCH MODULE 15.3 Bit Search Module Operation The bit search module performs the following three operations: • 0 detection • 1 detection • Change point detection ■ 0 Detection The bit search module scans data written to the 0 detection data register from the MSB to LSB and returns the location where the first "0"...

  • Page 468

    CHAPTER 15 BIT SEARCH MODULE ■ Change Point Detection The bit search module scans data written to the change point detection data register from bit30 to the LSB for comparison with the MSB value. The first location where a value that is different from that of the MSB is detected is returned.

  • Page 469: Chapter 16 I 2 C Interface

    CHAPTER 16 I C INTERFACE This chapter describes the overview of the I C interface, the configuration and functions of registers, and I C interface operation. 16.1 Overview of the I C Interface 16.2 I C Interface Registers 16.3 Block Diagram of I C Interface 16.4 Detailed on Registers of the I C Interface...

  • Page 470: Overview Of The I C Interface

    CHAPTER 16 I C INTERFACE 16.1 Overview of the I C Interface This section explains the overview of the I C interface. ■ Overview The I C interface is a serial I/O port that supports INTER IC bus. The I C interface serves as a master or slave device on the I C bus and has the following features:...

  • Page 471: I 2 C Interface Registers

    CHAPTER 16 I C INTERFACE 16.2 I C Interface Registers This section describes the registers of the I C interface. ■ I C Interface Registers ❍ Bus control register (IBCR0/IBCR1) Address: 000094 /0000B4 BEIE GCAA INTE Initial value => ❍ Bus status register (IBSR0/IBSR1) Address: 000095 /0000B5 Initial value =>...

  • Page 472

    CHAPTER 16 I C INTERFACE ❍ 7-bit slave address register (ISBA0/ISBA1) Address: 00009B /0000BB Initial value => ❍ 7-bit slave address mask register (ISMK0/ISMK1) Address: 00009A /0000BA ENSB Initial value => ❍ Data register (IDAR0/IDAR1) Address: 00009D /0000BD Initial value => ❍...

  • Page 473: Block Diagram Of I 2 C Interface

    CHAPTER 16 I C INTERFACE 16.3 Block Diagram of I C Interface This section shows the block diagram of the I C interface. ■ Block Diagram (for 1 channel) Figure 16.3-1 Block Diagram of the I C Interface ICCR C operation enable IDBL Clock enable CLKP...

  • Page 474: Detailed On Registers Of The I C Interface

    CHAPTER 16 I C INTERFACE 16.4 Detailed on Registers of the I C Interface This section describes the detailed register of the I C interface. ■ Bus Status Register (IBSR0/IBSR1) Address: 000095 /0000B5 Initial value=> This register is read only. All bits are cleared when the I C stops operating (EN = 0 in ICCR).

  • Page 475

    CHAPTER 16 I C INTERFACE [bit3] TRX (Transferring Data) This bit indicates the transmission status during a data transfer. Data transmission stopped Data transmission in progress This bit is set to "1" if: • A START condition occurs in master mode. •...

  • Page 476

    CHAPTER 16 I C INTERFACE • Writing "0" to the MSS bit during master interrupt: (MSS=1, INT=1: IBCR) • Writing "1" to the SCC bit during master interrupt: (MSS=1, INT=1: IBCR) • Clearing the INT bit • Beginning of a transfer byte that is not used for the transfer target as master or slave ■...

  • Page 477

    CHAPTER 16 I C INTERFACE [bit13] SCC (Start Condition Continue) This bit is the repeated [START] condition generation bit. During writing Irrelevant Generates a repeated START condition in master transfer. The read value of this bit is always "0". If "1" is written to this bit in master mode (MSS = 1 and INT = 1) a repeated START condition is generated, the INT bit is automatically cleared.

  • Page 478

    CHAPTER 16 I C INTERFACE [bit11] ACK (ACKnowledge) This bit generates an acknowledge according to the setting of the data receive enable bit. Acknowledge not generated when data is received Acknowledge generated when data is received This bit is disabled when slave address data is received in slave mode. An acknowledge is returned if the I C interface detects a 7-bit or 10-bit slave address when the corresponding enable bits (ENTB: ITMK, ENSB: ISMK) are set.

  • Page 479

    CHAPTER 16 I C INTERFACE During reading • Transfer not ended • Not a transfer target • Bus is open. This bit is set to "1" if a one-byte transfer that includes the acknowledge bit is completed and the following conditions are met: •...

  • Page 480

    CHAPTER 16 I C INTERFACE Figure 16.4-1 Diagram of Timing at which an Interrupt upon Detection of "AL Bit = 1" does not Occur "L" SCL pin "L" SDA pin C operating enable state (EN bit = 1) Master mode setting (MSS bit = 1) Arbitration lost detection (AL bit = 1) Bus busy (BB bit ) Interrupt (INT bit )

  • Page 481

    CHAPTER 16 I C INTERFACE Example in which an interrupt (INT bit = 1) upon detection of "AL bit = 1" occurs When an instruction which generates a start condition is executed (setting "1" to the MSS bit) with the bus busy detected (BB = 1) and the arbitration lost is performed, the INT bit interrupt is generated upon detection of AL bit =1.

  • Page 482

    CHAPTER 16 I C INTERFACE A sample flow is given below. Master mode setting Set the MSS bit in the bus control register (IBCR) to "1". Wait * for the time for three-bit data transmission at the I transfer frequency set in the clock control register (ICCR). BB bit = 0 and AL bit = 1? To normal process Set the EN bit to "0"...

  • Page 483

    CHAPTER 16 I C INTERFACE [bit12 to bit8] CS4 to CS0 (Clock Period Select 4 to 0) These bits set the frequency of the serial clock. These bits can be written only when operation is disabled (EN=0) or the EN bit is cleared. The frequency of the shift clock, fsck, which is calculated as shown below.

  • Page 484

    CHAPTER 16 I C INTERFACE ■ 10-bit Slave Address Register (ITBA0/ITBA1) Address: 000096 /0000B6 ITBAH Initial value => Address: 000097 /0000A7 ITBAL Initial value => Rewrite this register while operation is disabled (EN=0: ICCR). [bit15 to bit10] (Reserved) The values read from these bits are "0". [bit9 to bit0] 10-bit slave address bits (A9 to A0) If a 10-bit address is enabled (ENTB=1: ITMK), slave address data is received in the slave mode and then compared with the ITBA.

  • Page 485

    CHAPTER 16 I C INTERFACE [bit14] RAL (Slave address length bit) This bit indicates the slave address length. 7-bit slave address 10-bit slave address If the 10-bit and 7-bit slave address enable bits are both enabled (ENTB=1 and ENSB=1), this bit can be used to determine whether the transfer length of a 10-bit or 7-bit slave address becomes valid.

  • Page 486

    CHAPTER 16 I C INTERFACE The I C interface returns an acknowledge in response to reception of the address header of a 7-bit read access after a repeated START condition is generated. All bits of a slave address are masked using of the ISMK. The received slave address data is overwritten to the ISBA register.

  • Page 487

    CHAPTER 16 I C INTERFACE ■ Data Register (IDAR0/IDAR1) Address: 00009D /0000BD Initial value=> [bit7 to bit0] Data bits (D7 to D0) Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB. Since the writing side of this register has double buffers, write data is loaded into the register for serial transfer while the bus is being used (BB=1).

  • Page 488: I 2 C Interface Operation

    CHAPTER 16 I C INTERFACE 16.5 I C Interface Operation This section explains the operation of the I C interface. ■ Operational Explanation The I C bus consists of two bidirectional bus lines used for transfer: one serial data line (SDA) and one serial clock line (SCL).

  • Page 489

    CHAPTER 16 I C INTERFACE ❍ Slave Address Detection In slave mode, BB=1 is set after a START condition is generated. The receive data from the master device is stored in the IDAR register. When a 7-bit slave address is enabled (ISMK ENSB=1) After 8-bit data is received, the IDAR and ISBA register values are compared.

  • Page 490

    CHAPTER 16 I C INTERFACE ❍ Master Addressing In master mode, BB=1 and TRX=1 are set after a START condition is generated and the IDAR register value is sent starting with the MSB. After address data is sent and an acknowledge is received from a slave device, bit0 of the send data (bit0 of the IDAR register after transmission) is inverted and stored in the TRX bit.

  • Page 491

    CHAPTER 16 I C INTERFACE ❍ Communication Error that Causes No Errors If, during transmission in master mode, an illegal clock is generated on the SCL line due to noise or for some other reason, the transmission bit counter of the I C interface may run quickly, causing the slave to hang while L has appeared on the SDA line in the ACK cycle.

  • Page 492

    CHAPTER 16 I C INTERFACE ❍ Other Items 1. Addressing after arbitration lost occurs After arbitration lost occurs, check whether or not the local device is addressed using software. When arbitration lost occurs, the device becomes a slave in terms of hardware. However, after one-byte transfer is completed, both the CLK and DATA lines are set to "L"...

  • Page 493: Operation Flowcharts

    CHAPTER 16 I C INTERFACE 16.6 Operation Flowcharts This section provides the operation flowcharts for the I C interface. ■ Example of Slave Address and Data Transfer Figure 16.6-1 Example of Slave Address and Data Transfer Transfer data 7-bit slave addressing Start Start Slave address in...

  • Page 494

    CHAPTER 16 I C INTERFACE Figure 16.6-2 Example of Receive Data Start Slave address in read access Clear the ACK bit if data is the last read data from the slave. INT = 0 INT=1? Restart BER=1? bus error Transfer of last byte Transfer completed...

  • Page 495

    CHAPTER 16 I C INTERFACE Figure 16.6-3 Interrupt Processing START Receive INT=1? interrupt from another module Restart BER=1? bus error GCA=1? General call detected in slave mode Failure of transfer Retry AAS=1? Retransfer AL=1? AL=1? arbitration lost No ACK from slave. Generate STOP LRB=1? condition or repeated...

  • Page 496

    CHAPTER 16 I C INTERFACE...

  • Page 497: Chapter 17 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER This chapter gives an overview of the 16-bit free run timer, the configuration and functions of its registers, and its operation. 17.1 Overview of 16-bit Free Run Timer 17.2 Registers of the 16-bit Free Run Timer 17.3 Block Diagram of the 16-bit Free Run Timer 17.4 Details on Registers of the 16-bit Free Run Timer 17.5 Operation of the 16-bit Free Run Timer...

  • Page 498: Overview Of 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER 17.1 Overview of 16-bit Free Run Timer This section explains the overview of the 16-bit free run timer ■ Overview The 16-bit free run timer consists of a 16-bit up counter and control status register. The count values of this timer are used as a base timer for output compare and input capture operations.

  • Page 499: Registers Of The 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER 17.2 Registers of the 16-bit Free Run Timer This section explains the registers of the 16-bit free run timer. ■ Registers of 16-bit Free Run Timer Figure 17.2-1 Registers of Multifunctional Timer bit15 Timer data register (high-order bits) (TCDT) bit 7...

  • Page 500: Block Diagram Of The 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER 17.3 Block Diagram of the 16-bit Free Run Timer This section shows the block diagram of the 16-bit free run timer. ■ Block Diagram of the 16-bit Free Run Timer Figure 17.3-1 Block Diagram of the 16-bit Free Run Timer Interrupt ECLK IVFE...

  • Page 501: Details On Registers Of The 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER 17.4 Details on Registers of the 16-bit Free Run Timer This section details the registers of the 16-bit free run timer. ■ Timer Data Register (TCDT) TCDT bit 15 Address: 0000D4 Initial value 0000 bit 7 This register allows reading the count value of the 16-bit free run timer.

  • Page 502

    CHAPTER 17 16-BIT FREE RUN TIMER ■ Timer Control Status Register (TCCS) TCCS bit 7 Address: 0000D7 ECLK IVFE STOP MODE CLK1 CLK0 Initial value [bit7]: ECLK This bit selects the internal or external count clock source of the 16-bit free run timer. The clock is changed immediately after writing to this bit.

  • Page 503

    CHAPTER 17 16-BIT FREE RUN TIMER [bit4]: STOP This bit is used to stop the count of the 16-bit free run timer. When the bit is set to "1", the count of the timer is stopped. When the bit is set to "0", the count of the timer is started. STOP Count operation Allows counting (operation) (initial value)

  • Page 504

    CHAPTER 17 16-BIT FREE RUN TIMER [bit1, bit0]: CLK1, CLK0 These bits are used to select a count clock for the 16-bit free run timer. Immediately after these bits are set to a new value, the clock is switched. Therefore, change these bits while the output compare and input capture are stopped.

  • Page 505: Operation Of The 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER 17.5 Operation of the 16-bit Free Run Timer This section explains the operation of the 16-bit free run timer. ■ Operational Explanation The 16-bit free run timer starts counting from the counter value "0000 "...

  • Page 506

    CHAPTER 17 16-BIT FREE RUN TIMER Figure 17.5-2 Clearing the Counter when the Counter Value Matches that of the Compare Clear Register Counter value FFFF Match Match BFFF 7FFF 3FFF Time 0000 Reset Compare register BFFF Interrupt ❍ Timing to Clear the 16-bit Free Run Timer The counter is cleared by reset, software, or when the counter value matches that of the compare clear register.

  • Page 507: Precautions On Using The 16-bit Free Run Timer

    CHAPTER 17 16-BIT FREE RUN TIMER 17.6 Precautions on Using the 16-bit Free Run Timer This section gives notes on the 16-bit free run timer. ■ Notes 1. If the interrupt request flag set timing and clear timing are simultaneously generated, the flag setting operation overrides the flag clearing operation.

  • Page 508

    CHAPTER 17 16-BIT FREE RUN TIMER...

  • Page 509: Chapter 18 Input Capture

    CHAPTER 18 INPUT CAPTURE This chapter explains the overview of the input capture, the configuration and functions of its registers, and its operation. 18.1 Overview of Input Capture 18.2 Input Capture Registers 18.3 Block Diagram of Input Capture 18.4 Details on Registers of Input Capture 18.5 Operation of Input Capture...

  • Page 510: Overview Of Input Capture

    CHAPTER 18 INPUT CAPTURE 18.1 Overview of Input Capture This section explains the overview of the input capture. ■ Overview of Input Capture The input capture module detects either or both of the rising and falling edges of an externally input signal, and stores the 16-bit free run timer value set at that time in a register.

  • Page 511: Input Capture Registers

    CHAPTER 18 INPUT CAPTURE 18.2 Input Capture Registers This section shows the input capture registers. ■ Registers of the Input Capture Figure 18.2-1 Registers of the Input Capture Input capture data register CP15 CP14 CP13 CP12 CP11 CP10 CP09 CP08 (high-order bits) (IPCP) Input capture data register...

  • Page 512: Block Diagram Of Input Capture

    CHAPTER 18 INPUT CAPTURE 18.3 Block Diagram of Input Capture This section shows a block diagram of the input capture. ■ Block Diagram of the Input Capture Figure 18.3-1 Block Diagram of the Input Capture 16-bit timer count value (T15 to T00) ICU0, ICU2 Edge Capture data register...

  • Page 513: Details On Registers Of Input Capture

    CHAPTER 18 INPUT CAPTURE 18.4 Details on Registers of Input Capture This section describes the details on the registers of the input capture. The input capture has the following two data registers: • Input capture data registers (IPCP0 to IPCP3) •...

  • Page 514

    CHAPTER 18 INPUT CAPTURE [bit5, bit4]: ICE3, ICE2, ICE1, and ICE0 These bits are used as input-capture interrupt permission bits. When these bits are set to "1" and the interrupt flags (ICP3, ICP2, ICP1, and ICP0) are also set to "1", an input-capture interrupt occurs.

  • Page 515: Operation Of Input Capture

    CHAPTER 18 INPUT CAPTURE 18.5 Operation of Input Capture This section explains the operation of the input capture. ■ Operational Explanation When the set effective edge is detected, the 16-bit input capture can capture the 16-bit free run timer value to the capture register to generate an interrupt. ❍...

  • Page 516

    CHAPTER 18 INPUT CAPTURE ❍ Input Timing of 16-bit Input Capture Figure 18.5-2 Input Timing of Input Capture φ Counter value N + 1 Input capture input Effective edge Capture signal Capture register value N + 1 Interrupt...

  • Page 517: Chapter 19 Program Loader Mode (supported Only By The Mb91302a (ipl Integrated Model))

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) This chapter outlines the program loader mode and describes the settings for the program loader and operations in that mode. 19.1 Overview of the Program Loader Mode 19.2 Setting the Program Loader 19.3 Operations in the Program Loader Mode 19.4 Example of Using the Program Loader Mode to Write to Flash Memory...

  • Page 518: Overview Of The Program Loader Mode

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) 19.1 Overview of the Program Loader Mode This section gives an overview of the program loader mode. ■ Overview of the Program Loader Mode In the program loader mode, the program loader stored in the internal ROM uses UART ch.0 to perform serial communication with an external device, load a program from the external device to the internal RAM (2 Kbytes), and to start the loaded program.

  • Page 519: Setting The Program Loader

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) 19.2 Setting the Program Loader This section describes how to set the program loader. ■ Setting the Program Loader The program loader stored in internal ROM is started when the MD2, MD1, MD0, and SIN0 pins are set as in Table 19.2-1 during initialization by INIT.

  • Page 520: Operations In The Program Loader Mode

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) 19.3 Operations in the Program Loader Mode This section describes the operations for asynchronous communication and synchronous communication in the program loader mode. ■ Operations in the Program Loader Mode ❍...

  • Page 521

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ■ Commands Listed below are the commands issued to the FR and the response signals from the FR. Download (Reception) <- (PC, etc.) Command Reset (Reception) <- (PC, etc.) RAM Jump (Reception)

  • Page 522

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ■ Operation Example ❍ Transferring 0000005B - byte data to RAM address 00018000 Processing order PC,etc. Command Data -> (Reception) -> -> Download destination address (Reception) -> ->...

  • Page 523

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ■ Flowcharts ❍ Main program flowchart START Asynchronous SIN=L ? communication Synchronous Asynchronous Synchronous communication Set the gear ( CPU:13.5MHz / Peripheral:13.5MHz ) Set UART1 * MAIN Receive command other than 00 Received command = ?

  • Page 524

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "Command reception" in Asynchronous mode Receive command 1- byte data reception (command data) Receive Data ? 1 - byte data reception (command data) Received data = 18 RESET 8 - byte data reception (Download information data)

  • Page 525

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "DOWN LOAD" in Asynchronous mode DOWN LOAD 1 - byte transmission (Response to normal command reception) 1 - byte transmission ( 01 Download to internal RAM Receive Data ? 1 - byte data reception Increment the received data storage address...

  • Page 526

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "Command error" in Asynchronous mode 1 - byte transmission (Response to abnormal command reception) Error command Transmission data Fetch received command data { (received command data) & (F0 ) } | (04 1- byte transmission MAIN...

  • Page 527

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "Command Reception" in Synchronous mode Receive command 1- byte transmission (dummy) One - byte data reception (command data) Receive Data ? 1-byte data reception (command data) Received data = 18 RESET 1- byte transmission (dummy)

  • Page 528

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "DOWN LOAD" in Synchronous mode DOWN LOAD 1- byte transmission (Response to normal command reception) 1- byte transmission ( 01 Receive Data ? Receive dummy DOWNLOAD 1- byte transmission (dummy) Receive Data ?

  • Page 529

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "Command error" in Synchronous mode 1- byte transmission (Response to abnormal command reception) Error command Transmission data Fetch received command data { (received command data) & (F0 ) } | (04 1- byte transmission Receive Data ? Receive dummy...

  • Page 530

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) ❍ Subroutine "RESET" in Synchronous mode 1- byte transmission (Response to RESET command reception) RESET 1- byte transmission (11 Receive Data ? Receive dummy MAIN...

  • Page 531: Example Of Using The Program Loader Mode To Write To Flash Memory

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) 19.4 Example of Using the Program Loader Mode to Write to Flash Memory This section describes an example of connection when flash memory connected to CS0 is located and written by using the program loader mode. ■...

  • Page 532

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) Figure 19.4-2 A Memory Access with Offset Addresses Added (1 Mbyte) Same area can be accessed, whether 0FFFFC or 1FFFFC MB91302A (IPL integrated model) 1 Mbyte Flash D7 to D15 to D31 to D24...

  • Page 533

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL)) Figure 19.4-3 Memory Map for Each Mode External ROM, external bus mode Internal ROM, external bus mode (at executing loader program) (normal operating) 000000 Internal resource 000000 Internal resource Internal Internal RAM...

  • Page 534

    CHAPTER 19 PROGRAM LOADER MODE (SUPPORTED ONLY BY THE MB91302A (IPL INTEGRATED MODEL))

  • Page 535

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A- 010 USER'S GUIDE This chapter describes the features of the MB91302A-010 and its development methods. 20.1 Overview 20.2 Memory Map 20.3 Specifications for REALOS/FR Embedded in MB91302A-010 20.4 Section Allocation 20.5 Startup Routine 20.6 Initial Settings for SOFTUNE Workbench and REALOS/FR 20.7 Mode Pins, Mode Vectors, and Reset Vectors 20.8 Chip Evaluation System...

  • Page 536: Chapter 20 Real-time Os Embedded Mb91302a-010 User's Guide

    *1: TRON is an abbreviation of "The Real-time Operating System Nucleus". ITRON is an abbreviation of "Industrial TRON". µTRON is an abbreviation of "Micro Industrial TRON". *2: SOFTUNE is a trademark of FUJITSU LIMITED. REALOS is a trademark of FUJITSU LIMITED.

  • Page 537: Memory Map

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE 20.2 Memory Map This section provides memory maps of the MB91302A-010 and its evaluation chip MB91V301A. ■ Memory Map The following are memory maps for the MB91302A-010 and MB91V301A. The MB91302A-010 contains REALOS/FR conforming to µITRON 3.0 in the internal 4K byte ROM area located at addresses FF000 to FFFFF Figure 20.2-1 Memory Map of MB91302A-010 and MB91V301A...

  • Page 538: Specifications For Realos/fr Embedded In Mb91302a-010

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE 20.3 Specifications for REALOS/FR Embedded in MB91302A-010 The MB91302A-010 contains µITRON 3.0 compliant REALOS/FR in the internal 4 Kbytes ROM. This section describes the system calls and objects supported by REALOS/FR embedded in internal 4 Kbytes ROM. ■...

  • Page 539

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ■ Objects The MB91302A-010's internal ROM contains the following objects. The MB91302A-010 supports event flags, semaphores, and mailboxes. Table 20.3-3 Objects Objects Name Number of Definitions Event flag 0 to 32 Semaphore 0 to 32 Mailbox 0 to 32...

  • Page 540: Section Allocation

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE 20.4 Section Allocation This section describes section allocation. ■ Section Allocation The MB91302A-010 has the location address of the following section fixed. When developing an actual program, be sure to locate these sections at the following addresses. Sections are located through the project setting linker tab of SOFTUNE Workbench.

  • Page 541: Startup Routine

    REALOS/FR stored in internal ROM directly references the _uinit and _system_down labels defined in init_MB91302A-010_rtos.asm. Therefore, be sure to use init_MB91302A-010_rtos.asm provided by Fujitsu as the startup routine and do not modify the content. Updating the contents shifts the addresses of these labels referenced by REALOS/FR, preventing normal operation.

  • Page 542: Initial Settings For Softune Workbench And Realos/fr

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE 20.6 Initial Settings for SOFTUNE Workbench and REALOS/FR SOFTUNE Workbench and REALOS/FR are used to develop programs. This section describes initial settings for tools using practical examples. ■ Program Example The following sample program is discussed here to explain tool initialization. ❍...

  • Page 543

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ■ REALOS/FR Configurator Setup When you create a new project for REALOS/FR using SOFTUNE Workbench, the project appears with a member of "project-name.rcf" (hereafter called rcf file) in the REALOS directory of the project window. When you double-click on this rcf file to start Configurator and perform the initial setting of REALOS/FR.

  • Page 544

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ❍ Task definition tab Register user tasks. Start registration in order from ID number 1. Even though the number of user tasks for the actual system is less than 64, be sure to register 64 tasks. At this time, set the startup priority levels, stack, and initial state of unused user tasks using D'32 (minimum priority level), H'60 (minimum stack value acceptable), and DORMANT (idle state), respectively, not to start these empty user tasks.

  • Page 545

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ❍ Semaphore Definition Tab Register the semaphores to be used by the system. Register all of ID numbers 1 through 32 in ascending order. Even though the number of semaphores to be actually used is less than 32, be sure to register 32 semaphores.

  • Page 546

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE For this development example, the event flag definition tab of Configurator appears as shown below. Flag ID1 to ID16 Initial Pattern (P) -> H'0000 Flag ID17 to ID32 Initial Pattern (P) -> H'FFFF ❍...

  • Page 547

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ❍ Debug setting tab The MB91302A-010 has no unique setting. (Default setting) Note: At the default setting, the REALOS analyzer log function is restricted. MC FAMILY CONFORMING TO µITRON For more information, refer to the manual for FR-V/FR/F SPECIFICATIONS SOFTUNE REALOS ANALYZER MANUAL.

  • Page 548

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ■ Program Allocation The following describes program location. ❍ Section At least the following sections exist by default, including REALOS/FR. Table 20.6-10 Section Size Allocation top Section name Contents Memory (byte) address DATA Data in C source code Allocate freely...

  • Page 549

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE Figure 20.6-1 Linker Option and Address Map Address map Address Allocation option of the linker MB91302A- 010 Internal-4K byte ROM -sc oscode=0x000FF000 FF000 10000000 -sc sstack=0x10000000 -sc knldata1=0x10010000 -sc knldata2=0x10011F00 -sc DBGDAT2=0x10011FB0 -sc mplmem=0x10011FD0 External RAM -sc mplctl=0x10011FE0...

  • Page 550: Mode Pins, Mode Vectors, And Reset Vectors

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE 20.7 Mode Pins, Mode Vectors, and Reset Vectors This section describes the mode pins, mode vectors, and reset vectors of the MB91302A-010. For more information, see Sections "3.11.3 Reset Sequence" and "3.14 Operating Modes" as well. ■...

  • Page 551

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ■ Mode Data and Reset Vector Location Addresses The MB91302A-010 interrupt vector is sized 1 Kbyte and located in the R_eit section. Use the linker of SOFTUNE Workbench to locate the R_eit section at addresses 400FFC00 400FFFFF .

  • Page 552

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE ■ Fetching Mode Data and Reset Vectors after the Device is Released from a Reset The MB91302A-010 fetches the mode data and reset vector from addresses 000FFFF8 000FFFFC after being released from the reset. Depending on the next operation of the MB91302A-010, these items of data located at addresses 400FFFF8 and 400FFFFC in the...

  • Page 553

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE Figure 20.7-1 Example of Connection to External Memory Output the CS0 signal at access for all addresses after initialization by reset. Output each CS signal after CS initial setting of _csinit called from startup routine.

  • Page 554: Chip Evaluation System

    CHAPTER 20 REAL-TIME OS EMBEDDED MB91302A-010 USER'S GUIDE 20.8 Chip Evaluation System This section describes a sample configuration of the chip evaluation system. ■ Configuration Example :Target Board + Evaluation Chip + ICE Target board DSU cable USB or LAN Evaluation chip + adapter board + header board ( + RAM board) Name Type...

  • Page 555: Appendix

    APPENDIX This appendix consists of the following parts: I/O map, interrupt vector, pin states in each CPU state, notes on using a little endian area, and instruction lists. The appendix contains detailed information that could not be included in the main text and reference material for programming.

  • Page 556: Appendix A I/o Map

    APPENDIX A I/O MAP APPENDIX A I/O MAP Table A-1 shows the correspondence between the memory space area and the peripheral resource registers. ■ I/O Map [Reading the table] Register Block Address PDR0[R/W] PDR1[R/W] PDR2[R/W] PDR3[R/W] 000000 T-unit XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX Port Data Register...

  • Page 557

    APPENDIX A I/O MAP Table A-1 I/O Map (1 / 11) Register Address Block PDR0 [R/W] B PDR1 [R/W] B PDR2 [R/W] B − 000000 XXXXXXXX XXXXXXXX XXXXXXXX PDR6 [R/W] B − − − 000004 T-unit XXXXXXXX Port Data Register PDR8 [R/W] B PDR9 [R/W] B PDRA [R/W] B...

  • Page 558

    APPENDIX A I/O MAP Table A-1 I/O Map (2 / 11) Register Address Block SIDR1 [R] SSR1 [R/W] SCR1 [R/W] SMR1 [R/W] SODR1 [W] 000068 B,H,W B,H,W B,H,W UART1 B,H,W 00001000 00000100 00--0-0- XXXXXXXX UTIM1 [R] H,W UTIMC1 [R/W] DRCL1* 00006C (UTIMR1 [W] H,W) U-TIMER 1...

  • Page 559

    APPENDIX A I/O MAP Table A-1 I/O Map (3 / 11) Register Address Block IBCR1 [R/W] IBSR1 [R] ITBA1 [R/W] B,H,W 0000B4 B,H,W B,H,W 00000000 00000000 00000000 00000000 ISMK1 [R/W] ISBA1 [R,R/W] ITMK1 [R/W] B,H,W 0000B8 B,H,W B,H,W C interface1 00111111 11111111 00011111 00000000...

  • Page 560

    APPENDIX A I/O MAP Table A-1 I/O Map (4 / 11) Register Address Block PTMR2 [R] H PCSR2 [W] H,W 000130 11111111 11111111 XXXXXXXX XXXXXXXX PPG2 PDUT2 [W] H,W PCNH2 [R/W] B PCNL2 [R/W] B 000134 XXXXXXXX XXXXXXXX 00000000 000000X0 PTMR3 [R] H PCSR3 [W] H,W 000138...

  • Page 561

    APPENDIX A I/O MAP Table A-1 I/O Map (5 / 11) Register Address Block ISIZE [R/W] − 000304 B,H,W I-Cache ------10 000308 − Reserved 0003E0 ICHCR [R/W] − 0003E4 B,H,W I-Cache 0-000000 0003E8 − Reserved 0003EF BSD0 [W] W 0003F0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX BSD1 [R/W] W...

  • Page 562

    APPENDIX A I/O MAP Table A-1 I/O Map (6 / 11) Register Address Block ICR00 [R/W] ICR01 [R/W] ICR02 [R/W] ICR03 [R/W] 000440 B,H,W B,H,W B,H,W B,H,W ---11111 ---11111 ---11111 ---11111 ICR04 [R/W] ICR05 [R/W] ICR06 [R/W] ICR07 [R/W] 000444 B,H,W B,H,W B,H,W...

  • Page 563

    APPENDIX A I/O MAP Table A-1 I/O Map (7 / 11) Register Address Block STCR [R/W] RSRR [R/W] B,H,W TBCR [R/W] CTBR [W] B,H,W 00110011 B,H,W B,H,W 10000000 (INIT) 00XXXX00 XXXXXXXX 000480 (INIT) 0011XX11 (INIT) (INIT) -0-XX-00 (INIT) (INIT) 00XXXXXX XXXXXXXX XXX--X00 00X1XXXX...

  • Page 564

    APPENDIX A I/O MAP Table A-1 I/O Map (8 / 11) Register Address Block ACRH [R/W] ACR0L [R/W] ASR0 [R/W] H,W 000640 00000000 00000000 1111XX00 00000000 ACR1H [R/W] ACR1L [R/W] ASR1 [R/W] H,W 000644 B,H,W B,H,W XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX ACR2H [R/W] ACR2L [R/W] ASR2...

  • Page 565

    APPENDIX A I/O MAP Table A-1 I/O Map (9 / 11) Register Address Block IOWR0 [R/W] IOWR1 [R/W] − 000678 B,H,W B,H,W XXXXXXXX XXXXXXXX − 00067C TCR [R/W] B,H,W CSER [R/W] CHER [R/W] T-unit 00000000 − 000680 B,H,W B,H,W (INIT) 000000001 11111111 0000XXXX...

  • Page 566

    APPENDIX A I/O MAP Table A-1 I/O Map (10 / 11) Register Address Block EIA3 [W] W 000B2C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA4 [W] W 000B30 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA5 [W] W 000B34 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA6 [W] W 000B38 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX EIA7 [W] W...

  • Page 567

    APPENDIX A I/O MAP Table A-1 I/O Map (11 / 11) Register Address Block DMASA0 [R/W] W 001000 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA0 [R/W] W 001004 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA1 [R/W] W 001008 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMADA1 [R/W] W 00100C XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX DMASA2 [R/W] W...

  • Page 568: Appendix Binterrupt Vector

    APPENDIX B INTERRUPT VECTOR APPENDIX B INTERRUPT VECTOR Table B-1 shows the interrupt vector table, which gives the interrupt source and interrupt vector/interrupt control register allocations for the MB91301 series. ■ Interrupt Vectors Table B-1 Interrupt Vectors (1 / 4) Interrupt number Interrupt TBR default...

  • Page 569

    APPENDIX B INTERRUPT VECTOR Table B-1 Interrupt Vectors (2 / 4) Interrupt number Interrupt TBR default Interrupt source Offset level address Decimal Hexadecimal External Interrupt 5 ICR05 000FFFA8 − External Interrupt 6 ICR06 000FFFA4 − External Interrupt 7 ICR07 000FFFA0 Reload Timer 0 ICR08 000FFF9C...

  • Page 570

    APPENDIX B INTERRUPT VECTOR Table B-1 Interrupt Vectors (3 / 4) Interrupt number Interrupt TBR default Interrupt source Offset level address Decimal Hexadecimal − Time-base timer overflow ICR31 000FFF40 − C I/F0 ICR32 000FFF3C − C I/F1 ICR33 000FFF38 − Reserved for system ICR34 000FFF34...

  • Page 571

    APPENDIX B INTERRUPT VECTOR Table B-1 Interrupt Vectors (4 / 4) Interrupt number Interrupt TBR default Interrupt source Offset level address Decimal Hexadecimal − − Reserved for system 000FFED4 − − Reserved for system 000FFED0 − − Reserved for system 000FFECC −...

  • Page 572: Appendix C Pin State In Each Cpu State

    APPENDIX C PIN STATE IN EACH CPU STATE APPENDIX C PIN STATE IN EACH CPU STATE Table C-1 to Table C-4 list the pin states in each CPU state. ■ Meaning of Terms in the Pin State Table Terms related to the pin state have the following meanings: •...

  • Page 573

    APPENDIX C PIN STATE IN EACH CPU STATE ■ Pin State Table Table C-1 Pin States in External Bus 32-Bit Mode (1 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial...

  • Page 574

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-1 Pin States in External Bus 32-Bit Mode (2 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 575

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-1 Pin States in External Bus 32-Bit Mode (3 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 576

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-2 Pin States in External Bus 16-Bit Mode (1 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 577

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-2 Pin States in External Bus 16-Bit Mode (2 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 578

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-2 Pin States in External Bus 16-Bit Mode (3 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 579

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-3 Pin States in External Bus 8-Bit Mode (1 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 580

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-3 Pin States in External Bus 8-Bit Mode (2 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 581

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-3 Pin States in External Bus 8-Bit Mode (3 / 3) At initialization (INIT) Stop mode Function Bus open Specified Function name (BGRNT) Port Sleep Pin no. function name Initial name mode HIZ=0 HIZ=1...

  • Page 582

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-4 Pin States in Single Chip Mode (1 / 2) At initialization (INIT) Stop mode Function Initial value Specified name Pin no. Port name Sleep mode function name HIZ=0 HIZ=1 Internal ROM Bus width mode vector 8 bits...

  • Page 583

    APPENDIX C PIN STATE IN EACH CPU STATE Table C-4 Pin States in Single Chip Mode (2 / 2) At initialization (INIT) Stop mode Function Initial value Specified name Pin no. Port name Sleep mode function name HIZ=0 HIZ=1 Internal ROM Bus width mode vector 8 bits...

  • Page 584: Appendix Dnotes On Using A Little Endian Area

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA This section provides notes on the use of a little endian area classified with the following items: D.1 C Compiler (fcc911) D.2 Assembler (fasm911) D.3 Linker (flnk911) D.4 Debugger (sim911, eml911, mon911)

  • Page 585: C Compiler (fcc911)

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA C Compiler (fcc911) Note that when programming is done in the C language, behavior cannot be guaranteed if the following operations are performed for a little endian area: • Allocation of a variable with an initial value •...

  • Page 586

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA [Example] Assigning a structure to the structure variable little_st in a little endian area struct tag { char c; int i; } normal_st; extern struct tag little_st; #define STRMOVE(DEST,SRC) DEST.c=SRC.c;DEST.i=SRC.i; void main(void) { STRMOVE(little_st,normal_st);...

  • Page 587

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA ■ Specification of the -K lib Option When Using a String Manipulation Function If the -K lib option is specified, the compiler performs inline expansion for some of the string manipulation functions. At this point, processing may be changed to processing using halfwords or words as a way to select the optimum processing.

  • Page 588: Assembler (fasm911)

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA Assembler (fasm911) The following items regarding little endian areas need to be noted when the FR family assembly language is used for programming: • Section • Data access ■ Section A little endian area is primarily intended to be used for data exchange with CPUs with little endian lines.

  • Page 589

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA ■ Data Access When data in a little endian area is accessed, the data values can be coded without awareness of the endian method used. However, access to data in a little endian area must be performed using the same size as the data size.

  • Page 590: Linker (flnk911)

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA Linker (flnk911) The following items related to section allocation for linking need to be noted when a program that uses a little endian area is used: • Restriction on section types •...

  • Page 591: Debugger (sim911, Eml911, Mon911)

    APPENDIX D NOTES ON USING A LITTLE ENDIAN AREA Debugger (sim911, eml911, mon911) This section provides notes on using a simulator debugger or emulator debugger/ monitor debugger. ■ Simulator Debugger There is no memory space specification command that can indicate a little endian area. As a result, memory management commands and instructions executed to manage memory are handled as if they were big endian.

  • Page 592: Appendix Einstruction Lists

    APPENDIX E INSTRUCTION LISTS APPENDIX E INSTRUCTION LISTS This section provides lists of the FR family instructions. E.1 How to Read the Instruction Lists E.2 FR Family Instruction Lists...

  • Page 593: How To Read The Instruction Lists

    APPENDIX E INSTRUCTION LISTS How to Read the Instruction Lists Before the lists are presented, the following items are explained to make the lists easier to understand: • How to read the instruction lists • Addressing mode symbols • Instruction format ■...

  • Page 594

    APPENDIX E INSTRUCTION LISTS 6. Indicates a flag change. Flag change Flag meaning C: Change N: Negative flag -: No change Z: Zero flag 0: Clear V: Overflow flag 1: Set C: Carry flag 7. Instruction operation.

  • Page 595

    APPENDIX E INSTRUCTION LISTS ■ Addressing Mode Symbols Table E.1-1 Explanation of Addressing Mode Symbols (1 / 2) Symbol Meaning Register direct (R0 to R15, AC, FP, SP) Register direct (R0 to R15, AC, FP, SP) Register direct (R13, AC) Register direct (program status register) Register direct (TBR, RP, SSP, USP, MDH, MDL) Register direct (CR0 to CR15)

  • Page 596

    APPENDIX E INSTRUCTION LISTS Table E.1-1 Explanation of Addressing Mode Symbols (2 / 2) Symbol Meaning @(R14,disp8) Register relative indirect (disp8: -80 to 7F @(R15,udisp6) Register relative indirect (udisp6: 0 to 60, multiples of 4 only) @Ri+ Register indirect with post-increment (R0 to R15, AC, FP, SP) @R13+ Register indirect with post-increment (R13, AC) @SP+...

  • Page 597

    APPENDIX E INSTRUCTION LISTS ■ Instruction Format Table E.1-2 Instruction Format Type Instruction format 16 bits i8/o8 u4/m4 ADD, ADDN, CMP, LSL, LSR, ASR instructions only *C’ s5/u5 u8/rel8/dir/ reglist SUB-OP rel11...

  • Page 598: Fr Family Instruction Lists

    APPENDIX E INSTRUCTION LISTS FR Family Instruction Lists The FR family instruction lists are presented in the order listed below. ■ FR Family Instruction Lists Table E.2-1 "Add-Subtract Instructions" Table E.2-2 "Compare Instructions" Table E.2-3 "Logic Instructions" Table E.2-4 "Bit Manipulation Instructions" Table E.2-5 "Multiply Instructions"...

  • Page 599

    APPENDIX E INSTRUCTION LISTS ■ Add-Subtract Instructions Table E.2-1 Add-Subtract Instructions Mnemonic Type CYCLE NZVC Operation Remarks Rj, Ri CCCC Ri + Rj --> Ri *ADD #s5, Ri C’ CCCC Ri + s5 --> Ri The assembler treats the highest-order bit as the sign. #u4, Ri CCCC Ri + extu(i4) -->...

  • Page 600

    APPENDIX E INSTRUCTION LISTS ■ Logic Instructions Table E.2-3 Logic Instructions Mnemonic Type CYCLE NZVC Operation Remarks Rj, Ri CC-- &= Rj Word ❍ Rj, @Ri* 1+2a CC-- (Ri) &= Rj Word ❍ ANDH Rj, @Ri* 1+2a CC-- (Ri) &= Rj Halfword ❍...

  • Page 601

    APPENDIX E INSTRUCTION LISTS ■ Bit Manipulation Instructions Table E.2-4 Bit Manipulation Instructions Mnemonic Type CYCLE NZVC Operation Remarks ❍ BANDL #u4, @Ri 1+2a ---- (Ri)&=(0xF0+u4) Low-order 4 bits are manipulated. ❍ BANDH #u4, @Ri 1+2a ---- (Ri)&=((u4<<4)+0x0F) High-order 4 bits are manipulated.

  • Page 602

    APPENDIX E INSTRUCTION LISTS ■ Multiply Instructions Table E.2-5 Multiply Instructions Mnemonic Type CYCLE NZVC Operation Remarks Ri × Rj --> MDH,MDL 32bits × 32bits=64bits Rj,Ri CCC- Ri × Rj --> MDH,MDL MULU Rj,Ri CCC- No sign Ri × Rj --> MDL 16bits ×...

  • Page 603

    APPENDIX E INSTRUCTION LISTS ■ Shift Instructions Table E.2-6 Shift Instructions Mnemonic Type CYCLE NZVC Operation Remarks LSL Rj, Ri CC-C Ri << Rj --> Ri Logical shift LSL #u5, Ri (u5:0 to 31) CC-C Ri << u5 --> Ri LSL #u4, Ri CC-C Ri <<...

  • Page 604

    APPENDIX E INSTRUCTION LISTS ■ Memory Load Instructions Table E.2-8 Memory Load Instructions Mnemonic Type CYCLE NZVC Operation Remarks @Rj, Ri ---- (Rj) --> Ri @(R13,Rj), Ri ---- (R13+Rj) --> Ri @(R14,disp10), Ri ---- (R14+disp10) --> Ri @(R15,udisp6), Ri ---- (R15+udisp6) -->...

  • Page 605

    APPENDIX E INSTRUCTION LISTS ■ Memory Store Instructions Table E.2-9 Memory Store Instructions Mnemonic Type CYCLE NZVC Operation Remarks Ri, @Rj ---- Ri --> (Rj) Word Ri, @(R13,Rj) ---- Ri --> (R13+Rj) Word Ri, @(R14,disp10) ---- Ri --> (R14+disp10) Word Ri, @(R15,udisp6) ---- Ri -->...

  • Page 606

    APPENDIX E INSTRUCTION LISTS ■ Normal Branch (No Delay) Instructions Table E.2-11 Normal Branch (No Delay) Instructions Mnemonic Type CYCLE NZVC Operation Remarks 97-0 ---- Ri --> PC CALL label12 ---- PC+2-->RP , PC+2+(label12-PC-2)-->PC CALL @Ri 97-1 ---- PC+2-->RP ,Ri-->PC 97-2 ---- RP -->...

  • Page 607

    APPENDIX E INSTRUCTION LISTS Notes: • "2/1" under CYCLE indicates 2 when branching occurs and 1 when branching does not occur. • In the rel11 and rel8 fields of the hardware specifications, the assembler calculates values and sets them as shown below: (label12-PC-2)/2 -->...

  • Page 608

    APPENDIX E INSTRUCTION LISTS ■ Delayed Branch Instructions Table E.2-12 Delayed Branch Instructions Mnemonic Type CYCLE NZVC Operation Remarks JMP:D 9F-0 ---- Ri --> PC CALL:D label12 ---- PC+4 --> RP , PC+2+(label12-PC-2) --> PC CALL:D @Ri 9F-1 ---- PC+4 --> RP ,Ri --> PC RET:D 9F-2 ----...

  • Page 609

    APPENDIX E INSTRUCTION LISTS ■ Other Instructions Table E.2-13 Other Instructions Mnemonic Type CYCLE NZVC Operation Remarks 9F-A ---- No change ANDCCR #u8 CCCC CCR and u8 --> CCR ORCCR CCCC CCR or u8 --> CCR STILM ---- i8 --> ILM ILM immediate set ADDSP #s10 ----...

  • Page 610

    APPENDIX E INSTRUCTION LISTS Notes: • The number of execution cycles of LDM0(reglist) and LDM1(reglist) can be calculated as a*(n- 1)+b+1 cycles if the number of specified registers is n. • The number of execution cycles of STM0(reglist) and STM1(reglist) can be calculated as a*n+1 cycles if the number of specified registers is n.

  • Page 611

    APPENDIX E INSTRUCTION LISTS ■ 20-bit Normal Branch Macro Instructions Table E.2-14 20-bit Normal Branch Macro Instructions Mnemonic Operation Remarks *CALL20 label20,Ri Address of the next instruction --> RP, Ri: Temporary register (See Reference 1) label20 --> PC *BRA20 label20,Ri label20 -->...

  • Page 612

    APPENDIX E INSTRUCTION LISTS ■ 20-bit Delayed Branch Macro Instructions Table E.2-15 20-bit Delayed Branch Macro Instructions Mnemonic Operation Remarks *CALL20:D label20,Ri Address of the next instruction + 2 --> RP, Ri: Temporary register (See Reference 1) label20 --> PC *BRA20:D label20,Ri label20 -->...

  • Page 613

    APPENDIX E INSTRUCTION LISTS ■ 32-bit Normal Branch Macro Instructions Table E.2-16 32-bit Normal Branch Macro Instructions Mnemonic Operation Remarks *CALL32 label32,Ri Address of the next instruction --> RP, Ri: Temporary register (See Reference 1) label32 --> PC *BRA32 label32,Ri label32 -->...

  • Page 614

    APPENDIX E INSTRUCTION LISTS ■ 32-bit Delayed Branch Macro Instructions Table E.2-17 32-bit Delayed Branch Macro Instructions Mnemonic Operation Remarks *CALL32:D label32,Ri Address of the next instruction + 2 --> RP, Ri: Temporary register (See Reference 1) label32 --> PC *BRA32:D label32,Ri label32 -->...

  • Page 615

    APPENDIX E INSTRUCTION LISTS ■ Direct Addressing Instructions Table E.2-18 Direct Addressing Instructions Mnemonic Type CYCLE NZVC Operation Remarks DMOV @dir10, R13 ---- (dir10) --> R13 Word DMOV R13, @dir10 ---- R13 --> (dir10) Word DMOV @dir10, @R13+ ---- (dir10) --> (R13),R13+=4 Word DMOV @R13+, @dir10 ----...

  • Page 616

    APPENDIX E INSTRUCTION LISTS ■ Coprocessor Control Instructions Table E.2-20 Coprocessor Control Instructions Mnemonic Type CYCLE NZVC Operation Remarks COPOP #u4, #u8, CRj, CRi 9F-C ---- Operation instruction COPLD #u4, #u8, Rj, CRi 9F-D 1+2a ---- Rj --> CRi COPST #u4, #u8, CRj, Ri 9F-E 1+2a...

  • Page 617: Index

    INDEX INDEX The index follows on the next page. This is listed in alphabetic order.

  • Page 618

    INDEX Index Numerics 0 Detection A/D Converter 0 Detection ............447 A/D Converter (Sequential Conversion Type)..4 A/D Converter Registers........348 0 Detection Data Register Notes on Using the Internal DC-DC Regulator and 0 Detection Data Register (BSD0) ..... 445 A/D Converter ........

  • Page 619

    INDEX Area Configuration Registers Bit Search Module Bit Search Module ..........4 Configuration of Area Configuration Registers 0 to 7 (ACR0 to ACR7) ........ 152 Bit Search Module Registers......445 Block Diagram of the Bit Search Module....444 Area Select Registers Configuration of Area Select Registers 0 to 7 Block Diagram (ASR0 to ASR7) .........

  • Page 620

    INDEX Built-in Peripheral Request Chip Select Enable Register Built-in Peripheral Request ....... 408 Configuration of the Chip Select Enable Register (CSER) ..........172 Burst Access Functions of Bits in the Chip Select Enable Register Burst Access Operation........216 (CSER) ..........172 Burst Read/Write Operation CLKB Burst Read/Write Operation Timing....

  • Page 621

    INDEX Data Direction Registers Bit Configuration of the Control Status Register (TMCSR) ........... 272 Configuration of the Data Direction Registers (DDR) ..........261 Bit Functions of the Control Status Register (TMCSR) ........... 272 Data Format Detailed Bit of Control Status Register Data Format ..........184, 192 (ADCS)..........

  • Page 622

    INDEX DEOP Suppressing DMA..........419 Function of the DACK, DEOP,and DREQ Pins... 404 DMA Access Operation Timing of the DEOP Pin Output ......431 DMA Access Operation........236 Detection DMA Controller 0 Detection ............447 DMA Controller (DMAC) Registers ....386 0 Detection Data Register (BSD0) .....

  • Page 623

    INDEX DMASA Exception EIT (Exception,Interrupt,and Trap) ......79 Bit Configuration of Transfer Source/Transfer Operation of Undefined Instruction Exception ..92 Destination Address Setting Registers (DMASA0 to DMASA4/DMADA0 to External Bus Access DMADA4) ......... 400 External Bus Access .........187 Detailed Bit of Transfer Source/Transfer Destination External Bus Clock Address Setting Registers (DMASA0 to External Bus Clock (CLKT) ......107...

  • Page 624

    INDEX External Wait 16-bit Free Run Timer With External Wait........... 219 Operational Explanation ........485 Without External Wait ........218 Free Run Timer External Wait Cycle Timing Block Diagram of the 16-bit Free Run Timer..480 External Wait Cycle Timing ......209 Free Run Timer ...........

  • Page 625

    INDEX Immediate Set Immediate Set/16-bit/32-bit Immediate Transfer I Flag Instructions .........583 I Flag ..............81 Immediate Transfer Instructions I/O Circuit Types Immediate Set/16-bit/32-bit Immediate Transfer I/O Circuit Types ..........26 Instructions .........583 I/O Map INIT I/O Map ............536 Setting Initialization Reset (INIT) Clear I/O Pins Sequence ..........98 I/O Pins............

  • Page 626

    INDEX Instruction Cache Status External Interrupt Request Level ....... 322 Interrupt Number ..........328 Instruction Cache Status in Each Operating Mode ........... 58 Interrupt Sources and Timing Chart (PPG Output: Normal Polarity) ......... 301 Instruction Format Interrupt Stack ........... 83 Instruction Format ..........

  • Page 627

    INDEX ITMK Memory 10-bit Slave Address Mask Register Built-in Memory...........3 (ITMK0/ITMK1) ........ 464 Memory Connection Memory Connection Example......232 Memory Load Instructions Memory Load Instructions.........584 -K lib Option Memory Map Specification of the -K lib Option When Using a String Memory Map .......43, 73, 498, 517 Manipulation Function ......

  • Page 628

    INDEX Monitor Debugger Operation Emulator Debugger/Monitor Debugger ....571 Operation Timing of the WRn + Byte Control Type ..........204 Multiple Channels Activating Multiple Channels with the GCN ..303 Operation End Operation End/Stopping ........423 Multiply and Divide Registers Multiply and Divide Registers (MDH/MDL) ..

  • Page 629

    INDEX PCNL Power-on Bit Function of Control Status Registers External Clock Input after Power-on.....39 (PCNH,PCNL) ........286 Power-on Sequence ..........229 Control Status Registers (PCNH:PCNH3 to PCNH0, Processing after Power-on ........39 PCNL:PCNL3 to PCNL0)....286 PPG Cycle Set Register Bit Configuration of PPG Cycle Set Register (PCSR:PCSR3 to PCSR0) ....290 Configuration of the Pull-up Resistor Control Registers (PCR) ........

  • Page 630

    INDEX Program Example Program Status (PS) Register ......66 Program Example..........522 Register-to-Register Transfer Instructions Program Example of Smooth Startup and Stop of Register-to-Register Transfer Instructions ..585 Clock ..........129 Reload Operation Program Loader Reload Operation ........414, 418 Setting the Program Loader .......

  • Page 631

    INDEX RSRR Detailed Bit of Serial Mode Register (SMR) ..363 Reset Source Register/Watchdog Timer Control Serial Output Data Register Register (RSRR) ......... 110 Serial Input Data Register (SIDR)/Serial Output Data Register (SODR) .........368 Operation Initialization Reset (RST) ....95 Serial Status Register Operation Initialization Reset (RST) Clear Bit Configuration of Serial Status Register Sequence..........

  • Page 632

    INDEX Software Reset Successive Accesses Software Reset (STCR: SRST Bit Writing)... 96 Basic Timing (For Successive Accesses) .... 203 Source Clock Synchronous Reset Source Clock ........... 103 Synchronous Reset Operation ......101 Specifications Synchronous Write Enable Output Overview of Specifications ......... 51 Operation Timing for Synchronous Write Enable Output ..........

  • Page 633

    INDEX TMCSR Transfer Source/Transfer Destination Address Setting Register Bit Configuration of the Control Status Register (TMCSR) ........... 272 Bit Configuration of Transfer Source/Transfer Bit Functions of the Control Status Register Destination Address Setting Registers (TMCSR) ........... 272 (DMASA0 to DMASA4/DMADA0 to DMADA4)..........400 Detailed Bit of Transfer Source/Transfer Destination Bit Configuration of the 16-bit Timer Register...

  • Page 634

    INDEX Overview of the U-TIMER........ 308 U-TIMER (UTIM:UTIM2 to UTIM0)....309 U-TIMER Registers.......... 309 U-TIMER Control Register Bit Details of U-TIMER Control Register (UTIMC) ..........310 Precautions on the U-TIMER Control Register (UTIMC) ..........312 U-TIMER Control Register (UTIMC:UTIMC2 to UTIMC0) ...........

  • Page 635

    CM71-10114-4E FUJITSU SEMICONDUCTOR • CONTROLLER MANUAL FR60 32-BIT MICROCONTROLLER MB91301 Series HARDWARE MANUAL March 2007 the fourth edition FUJITSU LIMITED Electronic Devices Published Edited Business Promotion Dept.

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