Operation Of Wrn + Byte Control Type - Fujitsu FR60 Hardware Manual

CHAPTER 4 EXTERNAL BUS INTERFACE
4.5.2

Operation of WRn + Byte Control Type

This section shows the operation timing for the WRn + byte control type.
■ Operation Timing of the WRn + Byte Control Type
Figure 4.5-2 shows the operation timing for (TYP3 to TYP0 = 0010
Figure 4.5-2 Timing Chart for the WRn + Byte Control Type
READ
WRITE
• Operation of AS, CS, RD, A31 to A00, and D31 to D00 is the same as that described in
"4.5.1 Basic Timing".
• WR is asserted from the 2nd cycle of the bus access. Negation occurs after the wait cycle of
bits W15 to W12 of the AWR register is inserted. The timing of asserting RD and WR0 to
WR3 can be delayed by one cycle by setting the W01 bit of the AWR register to "1".
(Operation is the same as that for WR0 to WR3 described in "4.5.1 Basic Timing".)
204
MCLK
A31 to A00
AS
CSn
RD
WR0,WR1
WR2,WR3
D31 to D00
WR
WR0,WR1
WR2,WR3
D31 to D00
, AWR = 0008 ).
B H