Table Of Contents - Fujitsu FR60 Hardware Manual

CONTENTS
CHAPTER 1 OVERVIEW ................................................................................................... 1
1.1 Features of the MB91301 Series ........................................................................................................ 2
1.2 Block Diagram .................................................................................................................................... 7
1.3 Package Dimensions .......................................................................................................................... 8
1.4 Pin Layout ......................................................................................................................................... 11
1.5 Pin No. Table .................................................................................................................................... 13
1.6 List of Pin Functions ......................................................................................................................... 15
1.7 I/O Circuit Types ............................................................................................................................... 26
CHAPTER 2 HANDLING THE DEVICE .......................................................................... 31
2.1 Precautions on Handling the Device ................................................................................................. 32
2.2 Precautions on Handling Power Supplies ......................................................................................... 39
CHAPTER 3 CPU AND CONTROL UNITS ..................................................................... 41
3.1 Memory Space .................................................................................................................................. 42
3.2 Internal Architecture .......................................................................................................................... 45
3.3 Instruction Cache .............................................................................................................................. 50
3.3.1 Configuration of the Instruction Cache ........................................................................................ 51
3.3.2 Configuration of the Control Registers ........................................................................................ 54
3.3.3 Instruction Cache Statuses and Settings ..................................................................................... 58
3.3.4 Setting up the Instruction Cache before Use ............................................................................... 60
3.4 Dedicated Registers ......................................................................................................................... 63
3.4.1 Program Status (PS) Register ..................................................................................................... 66
3.5 General-Purpose Registers .............................................................................................................. 70
3.6 Data Structure ................................................................................................................................... 71
3.7 Word Alignment ................................................................................................................................ 72
3.8 Memory Map ..................................................................................................................................... 73
3.9 Branch Instructions ........................................................................................................................... 74
3.9.1 Operation of Branch Instructions with Delay Slot ........................................................................ 75
3.9.2 Operation of Branch Instruction without Delay Slot ..................................................................... 78
3.10 EIT (Exception, Interrupt, and Trap) ................................................................................................. 79
3.10.1 EIT Interrupt Levels ..................................................................................................................... 80
3.10.2 Interrupt Control Register (ICR) ................................................................................................... 82
3.10.3 System Stack Pointer (SSP) ........................................................................................................ 83
3.10.4 Table Base Register (TBR) ......................................................................................................... 84
3.10.5 Multiple EIT Processing ............................................................................................................... 88
3.10.6 EIT Operations ............................................................................................................................ 90
3.11 Reset (Device Initialization) .............................................................................................................. 94
3.11.1 Reset Levels ................................................................................................................................ 95
3.11.2 Reset Sources ............................................................................................................................. 96
3.11.3 Reset Sequence .......................................................................................................................... 98
3.11.4 Oscillation Stabilization Wait Time .............................................................................................. 99
3.11.5 Reset Operation Modes ............................................................................................................. 101
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