Fujitsu FR60 Hardware Manual page 212

32-bit microcontroller mb91301 series
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CHAPTER 4 EXTERNAL BUS INTERFACE
■ Data Format
The relationship between the internal register and external data bus is as follows:
❍ Word access (when executing the LD/ST instructions)
Figure 4.4-14 Relationship between the Internal Register and External Data Bus for Word Access
❍ Halfword access (when executing the LDUH/STH instructions)
Figure 4.4-15 Relationship between Internal Register and External Data Bus for Halfword Access
a) Output address low-order digits "00
Internal register External bus
❍ Byte access (when executing the LDUB/STB instructions)
Figure 4.4-16 Relationship between Internal Register and External Data Bus for Byte Access
a) Output address
low-order digits "00
"
B
Internal
External
register
bus
D31
D31
AA
D23
D23
D15
D15
D7
D7
AA
D0
D0
192
Internal register
D31
D23
D15
D7
D0
D31
D31
BB
D23
D23
AA
D15
D15
AA
D7
D7
BB
D0
D0
b) Output address
low-order digits "01
Internal
External
register
bus
D31
D23
AA
D15
D7
AA
D0
External bus
D31
AA
DD
D23
BB
CC
D15
BB
CC
D7
DD
AA
D0
"
b) Output address l ow-order digits "10
B
Internal register External bus
D31
D23
D15
AA
D7
BB
D0
c) Output address
"
low-order digits "10
B
Internal
External
register
bus
D31
D31
D23
D23
D15
D15
AA
D7
D7
AA
D0
D0
"
B
D31
D23
D15
BB
D7
AA
D0
d) Output address
"
low-order digits "11
B
Internal
External
register
bus
D31
D31
D23
D23
D15
D15
D7
D7
AA
AA
D0
D0
"
B
D31
D23
D15
D7
D0

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