Fujitsu FR60 Hardware Manual page 487

■ Data Register (IDAR0/IDAR1)
Address: 00009D
[bit7 to bit0] Data bits (D7 to D0)
Bits D7 to D0 are a data register used for serial transfer. Data is transferred from the MSB.
Since the writing side of this register has double buffers, write data is loaded into the register
for serial transfer while the bus is being used (BB=1). When the INT bit (IBCR) is cleared or
the bus is idle (BB = 0: IBSR), the transfer data is loaded into the internal transfer register.
Since, during reading, data is directly read from the register for serial transfer, receive data is
valid only while the INT bit (IBCR) is set.
■ Clock Disable Register (IDBL0/IDBL1)
Address: 00009F
[bit0] Clock disable bit (DBL)
This bit specifies whether to supply or stop supply of the operating clock for the I
This bit can be used in low-power consumption mode.
0
1
This bit is initialized to "0" by a reset. When "1" is written to this bit, the read value except this
register (IBDL) is undefined and writing to other than this bit (this register) is invalid.
Note:
When this bit is set to "1", I
bit 7 6
/0000BD
D7 D6
H H
R/W R/W
Initial value=> 0 0
bit 7 6
/0000BF
- -
H H
R R
Initial value=> 0 0
Supplies the clock for I
Stops supply of the clock for I
2
C immediately stops even if send and receive operation is in progress.
CHAPTER 16 I
5 4 3
D5 D4 D3
R/W R/W R/W R/W
0 0 0
5 4 3
- - -
R R R
0 0 0
2
C.
2 2
C. The I C line is opened.
2
C INTERFACE
2 1 0
D2 D1 D0
R/W R/W
0 0 0
2 1 0
- - DBL
R R R/W
0 0 0
2
C interface.
467