Block Diagram - Fujitsu FR60 Hardware Manual

1.2

Block Diagram

Figure 1.2-1 are the block diagram of the MB91301 series.
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Block Diagram
MB91302A
MB91V301A
MB91302A
MB91V301A : RAM 8K bytes
X0, X1
MD0 to MD2
INIT
INT0 to INT7
NMI
SIN0 to SIN2
SOT0 to SOT2
SCK0 to SCK2
AN0 to AN3
ATG
AVRH, AV
CC
AV /AVRL
SS
TIN0 to TIN2
* : ROM has non-ROM model, the optimum real time OS internal model, and the IPL (Internal Program
Loader) internal model by adding the user ROM model.
Figure 1.2-1 Block Diagram
32
Bit search
: RAM 4K bytes
: RAM 8K bytes (stack)
: ROM 4K bytes*
32
32 ↔ 16
Adapter
Clock
control
16
Interrupt
controller
8 ch
External interrupts
3 ch
UART
3 ch
U-TIMER
4 ch
A/D
3 ch
Reload timer
FR CPU
I-Cache 4K bytes
Core
32
DMAC 5 ch
Bus
Converter
32
External
memory I/F
SDRAM I/F
4 ch
PPG timer
Port I/F
2 ch
2
I C I/F
Free run timer
4 ch
ICU
CHAPTER 1 OVERVIEW
DREQ0,DREQ1
DACK0, DACK1
DEOP0, DEOP1
IOWR
IORD
A23 to A00
D31 to D16
D15 to D00
RD, WR
WR0 to WR3
CS0 to CS7
RDY
BRQ
BGRNT
SYSCLK
MCLK
AS
MCLKE
SRAS
SCAS
SWE
DQMUU, DQMUL
DQMLU, DQMLL
LBA
BAA
PPG0 to PPG3
TRG0 to TRG3
PORT
SDA0, SDA1
SCL0, SCL1
FRCK
ICU0 to ICU3
7