Write -> Write Operation - Fujitsu FR60 Hardware Manual

4.5.4 Write -> Write Operation
This section shows the operation timing for write -> write.
■ Write -> Write Operation
Figure 4.5-4 shows the operation timing for (TYP3 to TYP0=0000
MCLK
A31 to A00
AS
CSn
WRn
D31 to D00
• Setting of the W05/W04 bits of the AWR register enables 0 to 3 write recovery cycles to be inserted.
• After all of the write cycles, recovery cycles are generated.
• Write recovery cycles are also generated if write access is divided into phases for access
with a bus width wider than that specified.
Figure 4.5-4 Timing Chart for the Write -> Write Operation
Read Write recovery
CHAPTER 4 EXTERNAL BUS INTERFACE
, AWR=0018
B
Write
).
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