Fujitsu FR60 Hardware Manual page 242

CHAPTER 4 EXTERNAL BUS INTERFACE
starts at the new bank address. In SDRAM/FCRAM-connected areas, prefetch is also
temporarily stopped, even if the page address is undated when write access to a prefetched
area causes a page error or when access is made to another SDRAM/FCRAM area in which
prefetch is not enabled.
❍ Unit for one prefetch access operation
The unit for one prefetch access operation is determined by the DBW bits (bus width) and BST
bits (burst length).
Prefetch access always occurs with the full size of the bus width specified by the DBW bits and
access for the count of the burst length set by the BST bits in one access operation is
performed. That is, if any value other than "00
occurs in page mode/burst mode. Keep in mind whether ROM/RAM is conformable and enough
access time is applicable. (Set an appropriate value bits W15 to W08 bits of the AWR register).
During burst access, successive accesses occur only within the address boundary that is
determined by the burst length. Thus, if the boundary is crossed, for example, 4 bytes of free
space are available in the buffer, these 4 bytes cannot be accessed in one operation (If the
prefetch buffer starts at xxxxxx0E
bursts are set even though the bus width is 16 bits, only 2 bytes, xxxxxx0E
can be captured in the next prefetch access).
The following provides two examples:
• Area whose bus width is set to 16 bits and whose burst length is set to "2"
The amount of data read into the buffer in one prefetch operation is 4 bytes. In this case,
prefetch access is delayed until 4 bytes of free space are available in the prefetch buffer.
• Area whose bus width is set to 8 bits and whose burst length is set to "8"
The amount of data read into the buffer in one prefetch operation is 8 bytes. In this case,
prefetch access is delayed until 8 bytes of free space are available in the prefetch buffer.
❍ Burst length setting and prefetch efficiency
If requests for external bus access, other than prefetch access, to or errors in the prefetch buffer
occur during one operation of prefetch access as explained in the previous bullet, "Unit of one
prefetch access operation", these access requests must wait until access to the prefetch buffer
that is being executed is completed.
Thus, if the burst length is too long, the efficiency and reaction of bus access other than prefetch
may be degraded. If, on the other hand, the burst length is set to "1", many read cycles may be
wasted even if burst/page access memory is connected because single access is always
performed.
If settings are made so that the amount of data read in one prefetch access operation is large,
prefetch access can be started only after free space in the prefetch buffer for this amount is
available. Thus, access to the prefetch buffer is infrequent, and the external bus tends to be
idle. For example, if the bus width is set to 16 bits and the burst length is set to "8", the amount
of data read into the buffer in one prefetch operation is 16 bytes. Thus, a new prefetch access
can be started only after the prefetch buffer is completely empty.
Adjust the optimum burst length to suit use and the environment after taking the above into
consideration. Generally, when connecting asynchronous memory to which burst/page access
cannot be applied, it is best to set the burst length to "1" (single access). Conversely, when
memory whose burst/page access cycle is short is connected, it is better to set the burst length
to any value other than "1" (single access). In this case, it is best to make the setting so that 8
bytes (half of the buffer) are read in one read operation according to the bus width. However,
the optimum condition varies with the frequency of external access and varies with the
frequency divide-by rate setting of the external access clock.
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" is set for the BST bits, the prefetch always
B
, 4 bytes of free space are available in the buffer, and two
H
and xxxxxx0F ,
H H