Fujitsu FR60 Hardware Manual page 198

CHAPTER 4 EXTERNAL BUS INTERFACE
■ Bit Functions of the Refresh Control Register (RCR)
The following summarizes the functions of individual bits in the refresh control register (RCR).
[bit31] SELF (SELF refresh assert): Self-refresh control
This bit is used to control the self-refresh mode for memory that supports the self-refresh
mode.
Table 4.2-42 lists the settings for self-refresh control.
Table 4.2-42 Settings for Self-refresh Control
SELF
0
1
Setting the bit to "1" performs a self-refresh after issuing the SELF command. Writing "0"
terminates the self-refresh mode.
To hold the contents of SDRAM when putting the LSI into stop mode, use this bit to enter the
self-refresh mode before entering the stop mode. At this time, centralized refreshing is
performed before transition to the self-refresh mode. External access requests generated before
it is completed are put on hold. The mode transits to the stop mode.
The device is released from the self-refresh mode either when "0" is written to this bit or access
to SDRAM occurs. At this time, centralized refreshing is performed immediately after the
release. If external access such as SDRAM access is attempted, therefore, the external access
request is kept on hold and the CPU stops operation for a while. An attempt to put the LSI into
the stop mode when it cannot enter the self-refresh mode causes it to directly enter the power
save mode, resulting in corruption of data in SDRAM.
When read by a Read-modify-Write instruction, the SELF, RRLD, and PON bits always return to
"0".
[bit30] RRLD (Refresh counter ReLoaD): Refresh counter start control
This bit is used to start and reload the fresh counter.
Table 4.2-43 shows the function of refresh counter startup control.
Table 4.2-43 Function of Refresh Counter Startup Control
RRLD
0
1
The refresh counter is inactive in the initial state.
If this bit is set to "1" in this state, all the SDRAM areas currently enabled in the CSER are auto-
refreshed either once in distributed refresh mode or the RFC-specified number of times in
centralized refresh mode. After that, the values in the RFINT5 to RFINT0 bits are reloaded.
From then on, the refresh counter starts being decremented. Whenever the counter causes an
underflow from "000000
while at the same time auto-refreshing is performed once.
The bit returns to "0" upon completion of reloading.
To stop auto-refreshing, write "000000
When read by a Read-modify-Write instruction, the bit always returns "0".
178
Auto-refresh or power-down
Transition to self-refresh mode
Refresh counter startup control
Disable (no operation)
Execute auto-refreshing once and reload the RFINT value.
", repeatedly, the values in the RFINT5 to RFINT0 bits are reloaded
B
" to the RFINT5 to RFINT0 bits.
B
Self-refresh control