General Control Register 10 (Gcn10) - Fujitsu FR60 Hardware Manual

7.3.5

General Control Register 10 (GCN10)

The GCN10 selects the source of the PPG timer trigger input.
■ Bit Configuration of General Control Register 10 (GCN10)
The bit configuration of the GCN10 is shown below.
Figure 7.3-6 Bit Configuration of General Control Register 10 (GCN10)
Address: 000118
000119
■ Details of General Control Register 10 (GCN10)
[bit15 to bit12] TSEL33 to TSEL30: ch.3 trigger input selection bit
These bits are ch.3 trigger input select bits.
Table 7.3-11 Ch.3 Trigger Input Selection
0
0
0
0
0
0
0
1
1
1
1
1
bit 15 14 13
TSEL[33:30]
H
R/W R/W R/W
0 0 1
bit 7 6 5
TSEL[13:10]
H
R/W R/W R/W
0 0 0
TSEL33 to TSEL30
0 0
0 0
0 1
0 1
1 0
1 0
1 1
0 0
0 0
0 1
0 1
1 X
12 11 10 9
TSEL[23:20]
R/W R/W R/W R/W
1 0 0 1
4 3 2 1
TSEL[03:00]
R/W R/W R/W R/W
1 0 0 0
0 EN0 bit of GCN2
1 EN1 bit of GCN2
0 EN2 bit of GCN2
1 EN3 bit of GCN2 (initial value)
0 16-bit reload timer ch.0
1 16-bit reload timer ch.1
X Setting prohibited
0 External TRG0
1 External TRG1
0 External TRG2
1 External TRG3
X Setting prohibited
CHAPTER 7 PPG TIMER
8
←Attribute
R/W
←Initial value
0
0
←Attribute
R/W
←Initial value
0
Function
293