Fujitsu FR60 Hardware Manual page 601

■ Bit Manipulation Instructions
Table E.2-4 Bit Manipulation Instructions
Mnemonic
BANDL #u4, @Ri
BANDH #u4, @Ri
*1
BAND #u8, @Ri
BORL #u4, @Ri
BORLH #u4, @Ri
*2
BOR #u8, @Ri
BEORL #u4, @Ri
BEORH #u4, @Ri
*3
BEOR #u8, @Ri
BTSTL #u4, @Ri
BTSTH #u4, @Ri
*1: The assembler generates BANDL if the bit is set at u8&0F
In some cases, both BANDL and BANDH may be generated.
*2: The assembler generates BORL if the bit is set at u8&0F
In some cases, both BORL and BORH are generated.
*3: The assembler generates BEORL if the bit is set at u8&0F
In some cases, both BEORL and BEORH are generated.
Type OP CYCLE
C 80 1+2a
C 81 1+2a
C 90 1+2a
C 91 1+2a
C 98 1+2a
C 99 1+2a
C 88 2+a
C 89 2+a
APPENDIX E INSTRUCTION LISTS
NZVC Operation
---- (Ri)&=(0xF0+u4)
---- (Ri)&=((u4<<4)+0x0F)
---- (Ri)&=u8
---- (Ri) | = u4
---- (Ri) | = (u4<<4)
---- (Ri) | = u8
---- (Ri) ^ = u4
---- (Ri) ^ = (u4<<4)
---- (Ri) ^ = u8
0C-- (Ri) & u4
CC-- (Ri) & (u4<<4)
, and BANDH if the bit is set at u8&F0
H
, and BORH if the bit is set at u8&F0
H
, and BEORH if the bit is set at u8&F0
H
RMV Remarks
❍
Low-order 4 bits are
manipulated.
❍
High-order 4 bits
are manipulated.
-
❍
Low-order 4 bits are
manipulated.
❍
High-order 4 bits
are manipulated.
-
❍
Low-order 4 bits are
manipulated.
❍
High-order 4 bits
are manipulated.
-
- Low-order 4 bits are
tested.
- High-order 4 bits
are tested.
.
H
.
H
.
H
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