Dma Controller (Dmac) Registers - Fujitsu FR60 Hardware Manual

CHAPTER 14 DMA CONTROLLER (DMAC)

14.2 DMA Controller (DMAC) Registers

This section describes the configuration and functions of the registers used by the
DMA controller (DMAC).
■ DMA Controller (DMAC) Registers
Figure 14.2-1 shows the registers of the DMA controller (DMAC).
bit 31 24
ch.0
ch.0
ch.1
ch.1
ch.2
ch.2
ch.3
ch.3
ch.4
ch.4
ch.0
ch.0
ch.1
ch.1
ch.2
ch.2
ch.3
ch.3
ch.4
ch.4
386
Figure 14.2-1 DMA Controller (DMAC) Registers
23 16 15 8 7 0
Control/status register A
Control/status register B
Control/status register A
Control/status register B
Control/status register A
Control/status register B
Control/status register A
Control/status register B
Control/status register A
Control/status register B
DMAC all-channel control register
Transfer source address setting register
Transfer destination address setting register (DMADA0)
Transfer source address setting register
Transfer destination address setting register (DMADA1)
Transfer source address setting register
Transfer destination address setting register (DMADA2)
Transfer source address setting register
Transfer destination address setting register (DMADA3)
Transfer source address setting register
Transfer destination address setting register (DMADA4)
(DMACA0)
(DMACB0)
(DMACA1)
(DMACB1)
(DMACA2)
(DMACB2)
(DMACA3)
(DMACB3)
(DMACA4)
(DMACB4)
(DMACR)
(DMASA0)
(DMASA1)
(DMASA2)
(DMASA3)
(DMASA4)