2-Cycle Transfer (I/O -> External) - Fujitsu FR60 Hardware Manual

4.10.7 2-Cycle Transfer (I/O -> External)
This section explains 2-cycle transfer (I/O -> external) operation.
■ 2-Cycle Transfer (I/O -> External)
Figure 4.10-10 shows the operation timing chart for (TYP3 to TYP0=0000
IOWR=00
Figure 4.10-10 shows a case in which a wait is not set for memory and I/O.
Figure 4.10-10 Timing Chart for 2-Cycle Transfer (I/O -> External)
MCLK
A31 to A00
AS
CSn
WRn
CSn
RD
D31 to D00
DACKn
FR30
compatible
mode
DEOPn
DACKn
Basic
mode
DEOPn
DREQn
• The bus is accessed in the same way as an interface when the DMAC transfer is not
performed.
• In basic mode, DACKn/DEOPn is output both in the transfer source bus access and transfer
destination bus access.
).
H
I/O address
CHAPTER 4 EXTERNAL BUS INTERFACE
idle memory address
, AWR=0008 ,
B H
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