Fujitsu FR60 Hardware Manual page 25

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■ I
C Bus Interface
• 2-channel master/slave transmission and reception of I
• Arbitration function and clock synchronization function of I
■ Free Run Timer
• 16-bit 1channel
• Input capture 4 channels
■ Other Interval Timers
• 16-bit timer: 3 channels (U-TIMER)
• PPG timer: 4 channels
• Watchdog timer: 1 channel
■ Other Features
• Reset factor: Watchdog timer/software reset/external reset (INIT pin)
• Low-power consumption mode: sleep/stop mode
• Clock control
• Gear function
Allows arbitrary different operating clock frequencies to be set for the CPU and peripherals.
The gear clock factor can be selected from among 16 options: 1/1, 1/2, 1/3, 1/4, 1/5, 1/6, 1/7,
1/8,....., 1/16. Also, PLL multiplication can be selected. Note that the maximum operating
frequency of peripherals is 34 MHz.
• Packages: MB91302A FPT-144P-M12, FPT-144P-M08,
• CMOS technology
0.25 µm
•
• Power voltages
Power supply (analog power supply): 3.3 V ± 0.3 V (at using internal regulator)
•
• On chip Device Support Unit (DSU4) is installed in MB91V301A.
MB91V301A PGA-179C-A03
CHAPTER 1 OVERVIEW
2
C bus interface
2
C bus interface
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